tree 4bbfba4b281c3368c2544eafa1e93b63b517c509
parent c41ff6e5f38b02ff927d0d510e28dc1392bb4690
author Sergei Shtylyov <sshtylyov@ru.mvista.com> 1147796201 +0400
committer David Woodhouse <dwmw2@infradead.org> 1147796719 +0100

NAND: AMD Au1550 driver reads write-only register

     During the last cleanup of the AMD Au1550 NAND driver the old buglet was
reintroduced: as the MEM_STNDCTL register is write-only and seem to always
read as 0x31, read-modify-write to it done in au1xxx_nand_init() will have the
side effect of enabling -RCS0/1 pin override (via bits 4/5 of this reg.), thus
possibly causing a contention on the static bus when the NOR flash (using
-RCS0) or board control status registers (using -RCS2) are read. Luckily, this
goes away with a first NAND access, since au1550_hwcontrol() doesn't try to
read this register before writing anymore.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>