tg3: Add read accessor for AUX CTRL phy reg
This patch adds a read accessor for the aux ctrl register.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index dd331f8..b9382f1 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2194,19 +2194,22 @@
#define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */
+#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
+#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
+#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
+
+#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
#define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
#define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
#define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
-#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
-#define MII_TG3_AUXCTL_MISC_WREN 0x8000
-#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
-#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
+#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
+
#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
+#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
+#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
+#define MII_TG3_AUXCTL_MISC_WREN 0x8000
-#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
-#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
-#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
#define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */
#define MII_TG3_AUX_STAT_LPASS 0x0004