tree d92a548e536d704d76afa383285960f760e48751
parent a91de84b7874d5fa95477005179b66c97723bc36
author Siddhartha Agrawal <agrawals@codeaurora.org> 1409939094 -0700
committer Narendra Muppalla <NarendraM@codeaurora.org> 1484350881 -0800

clk: msm: mdss: Add support for DSI PLL 1 clock registration

Setup DSI 1 PLL clock heirarchy. This is needed for instances
where we need to turn off the second pll in case of current
leak issue.

Change-Id: I694af1fa9591b2345709687c9e7b1d69f15b56a9
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>