| commit | 178ca5312ad358fb129876bacbee8dac4681673a | [log] [tgz] |
|---|---|---|
| author | Chen-Yu Tsai <wens@csie.org> | Tue Jul 26 15:04:25 2016 +0800 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Mon Aug 08 20:03:20 2016 +0200 |
| tree | 3c179ffbc8f0e26e9bf6e757b85a0abdc85b364e | |
| parent | 29b4817d4018df78086157ea3a55c1d9424a7cfc [diff] |
clk: sunxi-ng: mux: Increase fixed pre-divider div size Some clocks have a predivider value that is larger than what u8 can store. One such example is the OUT clk found on A20/A31, which has a /750 pre-divider on one of the osc24M parents. Increase the size of the div field to u16. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>