ARM: dts: msm: clean up the dtsi for sensor modules
Rename the property name as part of clean-up work for sensor submodules.
Add new properties for regulator related control data
Change-Id: Ib5e707bf82b0ef71a1d1c66daaaa1652ffd9c30b
Signed-off-by: Alok Pandey <akumarpa@codeaurora.org>
diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
index ab6c835..cbd495a 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
@@ -22,12 +22,13 @@
compatible = "qcom,csiphy-v1.0", "qcom,csiphy";
reg = <0x0ac65000 0x1000>;
reg-names = "csiphy";
+ reg-cam-base = <0x65000>;
interrupts = <0 477 0>;
interrupt-names = "csiphy";
gdscr-supply = <&titan_top_gdsc>;
- qcom,cam-vreg-name = "gdscr";
- qcom,csi-vdd-voltage = <1200000>;
- qcom,mipi-csi-vdd-supply = <&pm8998_l26>;
+ regulator-names = "gdscr";
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&pm8998_l26>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
@@ -48,7 +49,8 @@
"csi0phytimer_clk",
"ife_0_csid_clk",
"ife_0_csid_clk_src";
- qcom,clock-rates =
+ clock-cntl-level = "turbo";
+ clock-rates =
<0 0 0 0 320000000 0 269333333 0 0 384000000>;
status = "ok";
};
@@ -58,12 +60,13 @@
compatible = "qcom,csiphy-v1.0", "qcom,csiphy";
reg = <0xac66000 0x1000>;
reg-names = "csiphy";
+ reg-cam-base = <0x66000>;
interrupts = <0 478 0>;
interrupt-names = "csiphy";
gdscr-supply = <&titan_top_gdsc>;
- qcom,cam-vreg-name = "gdscr";
- qcom,csi-vdd-voltage = <1200000>;
- qcom,mipi-csi-vdd-supply = <&pm8998_l26>;
+ regulator-names = "gdscr";
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&pm8998_l26>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
@@ -84,7 +87,8 @@
"csi1phytimer_clk",
"ife_1_csid_clk",
"ife_1_csid_clk_src";
- qcom,clock-rates =
+ clock-cntl-level = "turbo";
+ clock-rates =
<0 0 0 0 320000000 0 269333333 0 0 384000000>;
status = "ok";
@@ -95,12 +99,13 @@
compatible = "qcom,csiphy-v1.0", "qcom,csiphy";
reg = <0xac67000 0x1000>;
reg-names = "csiphy";
+ reg-cam-base = <0x67000>;
interrupts = <0 479 0>;
interrupt-names = "csiphy";
gdscr-supply = <&titan_top_gdsc>;
- qcom,cam-vreg-name = "gdscr";
- qcom,csi-vdd-voltage = <1200000>;
- qcom,mipi-csi-vdd-supply = <&pm8998_l26>;
+ regulator-names = "gdscr";
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&pm8998_l26>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
@@ -121,7 +126,8 @@
"csi2phytimer_clk",
"ife_lite_csid_clk",
"ife_lite_csid_clk_src";
- qcom,clock-rates =
+ clock-cntl-level = "turbo";
+ clock-rates =
<0 0 0 0 320000000 0 269333333 0 0 384000000>;
status = "ok";
};
@@ -129,15 +135,16 @@
cam_cci: qcom,cci@ac4a000 {
cell-index = <0>;
compatible = "qcom,cci";
- reg = <0xac4a000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
+ reg = <0xac4a000 0x4000>;
reg-names = "cci";
- interrupts = <0 460 0>;
+ reg-cam-base = <0x4a000>;
interrupt-names = "cci";
+ interrupts = <0 460 0>;
status = "ok";
gdscr-supply = <&titan_top_gdsc>;
- qcom,cam-vreg-name = "gdscr";
+ regulator-names = "gdscr";
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
@@ -150,17 +157,19 @@
"cpas_ahb_clk",
"cci_clk",
"cci_clk_src";
- qcom,clock-rates = <0 0 0 0 0 37500000>;
- pinctrl-names = "cci_default", "cci_suspend";
+ src-clock-name = "cci_clk_src";
+ clock-cntl-level = "turbo";
+ clock-rates = <0 0 0 0 0 37500000>;
+ pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cci0_active &cci1_active>;
pinctrl-1 = <&cci0_suspend &cci1_suspend>;
gpios = <&tlmm 17 0>,
<&tlmm 18 0>,
<&tlmm 19 0>,
<&tlmm 20 0>;
- qcom,gpio-tbl-num = <0 1 2 3>;
- qcom,gpio-tbl-flags = <1 1 1 1>;
- qcom,gpio-tbl-label = "CCI_I2C_DATA0",
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 1 1 1>;
+ gpio-req-tbl-label = "CCI_I2C_DATA0",
"CCI_I2C_CLK0",
"CCI_I2C_DATA1",
"CCI_I2C_CLK1";