msm_serial: fix serial on trout
Set the mnd counter based on uartclk. This fixes a problem
on 7x30 where the uartclk is 19.2Mhz rather than the usual
4.8Mhz.
Trout incorrectly reports uartclk to be running at 19.2Mhz
It is actually running at 4.8Mhz. For trout force mnd
counter values as if uartclk was fed by tcxo/4.
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
[dwalker@codeaurora.org: inlined, moved into header, added comments.]
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
diff --git a/drivers/serial/msm_serial.c b/drivers/serial/msm_serial.c
index ecdc0fa..f8c816e 100644
--- a/drivers/serial/msm_serial.c
+++ b/drivers/serial/msm_serial.c
@@ -41,19 +41,6 @@
unsigned int imr;
};
-#define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port)
-
-static inline void msm_write(struct uart_port *port, unsigned int val,
- unsigned int off)
-{
- __raw_writel(val, port->membase + off);
-}
-
-static inline unsigned int msm_read(struct uart_port *port, unsigned int off)
-{
- return __raw_readl(port->membase + off);
-}
-
static void msm_stop_tx(struct uart_port *port)
{
struct msm_port *msm_port = UART_TO_MSM(port);
@@ -320,11 +307,7 @@
struct msm_port *msm_port = UART_TO_MSM(port);
clk_enable(msm_port->clk);
-
- msm_write(port, 0xC0, UART_MREG);
- msm_write(port, 0xB2, UART_NREG);
- msm_write(port, 0x7D, UART_DREG);
- msm_write(port, 0x1C, UART_MNDREG);
+ msm_serial_set_mnd_regs(port);
}
static int msm_startup(struct uart_port *port)
@@ -706,6 +689,8 @@
if (unlikely(IS_ERR(msm_port->clk)))
return PTR_ERR(msm_port->clk);
port->uartclk = clk_get_rate(msm_port->clk);
+ printk(KERN_INFO "uartclk = %d\n", port->uartclk);
+
resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(!resource))