ARM: PL08x: avoid duplicating registers in txd and phychan structures
As we now have all the code accessing the phychan {csrc,cdst,clli,cctl,
ccfg} members in one function, there's no point storing the data into
the struct. Get rid of the struct members. Re-order the register dump
in the dev_dbg() to reflect the order we write the registers to the DMA
device.
The txd {csrc,cdst,clli,cctl} values are duplicates of the lli[0]
values, so there's no point duplicating these either. Program the DMAC
registers directly from the lli[0] values.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index c025a4b..a1a18bd 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -193,33 +193,25 @@
{
struct pl08x_driver_data *pl08x = plchan->host;
struct pl08x_phy_chan *phychan = plchan->phychan;
- u32 val;
+ struct pl08x_lli *lli = &txd->llis_va[0];
+ u32 val, ccfg;
plchan->at = txd;
- /* Copy the basic control register calculated at transfer config */
- phychan->csrc = txd->csrc;
- phychan->cdst = txd->cdst;
- phychan->clli = txd->clli;
- phychan->cctl = txd->cctl;
-
/* Assign the signal to the proper control registers */
- phychan->ccfg = plchan->cd->ccfg;
- phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
- phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
+ ccfg = plchan->cd->ccfg;
+ ccfg &= ~(PL080_CONFIG_SRC_SEL_MASK | PL080_CONFIG_DST_SEL_MASK);
+
/* If it wasn't set from AMBA, ignore it */
if (txd->direction == DMA_TO_DEVICE)
/* Select signal as destination */
- phychan->ccfg |=
- (phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
+ ccfg |= phychan->signal << PL080_CONFIG_DST_SEL_SHIFT;
else if (txd->direction == DMA_FROM_DEVICE)
/* Select signal as source */
- phychan->ccfg |=
- (phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
- /* Always enable error interrupts */
- phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
- /* Always enable terminal interrupts */
- phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
+ ccfg |= phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT;
+
+ /* Always enable error and terminal interrupts */
+ ccfg |= PL080_CONFIG_ERR_IRQ_MASK | PL080_CONFIG_TC_IRQ_MASK;
/* Wait for channel inactive */
while (pl08x_phy_channel_busy(phychan))
@@ -227,19 +219,15 @@
dev_vdbg(&pl08x->adev->dev,
"WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
- "cctl=0x%08x, clli=0x%08x, ccfg=0x%08x\n",
- phychan->id,
- phychan->csrc,
- phychan->cdst,
- phychan->cctl,
- phychan->clli,
- phychan->ccfg);
+ "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
+ phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
+ ccfg);
- writel(phychan->csrc, phychan->base + PL080_CH_SRC_ADDR);
- writel(phychan->cdst, phychan->base + PL080_CH_DST_ADDR);
- writel(phychan->clli, phychan->base + PL080_CH_LLI);
- writel(phychan->cctl, phychan->base + PL080_CH_CONTROL);
- writel(phychan->ccfg, phychan->base + PL080_CH_CONFIG);
+ writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
+ writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
+ writel(lli->lli, phychan->base + PL080_CH_LLI);
+ writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
+ writel(ccfg, phychan->base + PL080_CH_CONFIG);
/* Enable the DMA channel */
/* Do not access config register until channel shows as disabled */
@@ -920,13 +908,6 @@
*/
llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
- /* Now store the channel register values */
- txd->csrc = llis_va[0].src;
- txd->cdst = llis_va[0].dst;
- txd->clli = llis_va[0].lli;
- txd->cctl = llis_va[0].cctl;
- /* ccfg will be set at physical channel allocation time */
-
#ifdef VERBOSE_DEBUG
{
int i;