| commit | 196de71a9d9e9090406a87362d22b67ae633fa7a | [log] [tgz] |
|---|---|---|
| author | James Liao <jamesjj.liao@mediatek.com> | Fri Jul 10 16:39:33 2015 +0800 |
| committer | Stephen Boyd <sboyd@codeaurora.org> | Tue Jul 28 11:58:54 2015 -0700 |
| tree | 615be1dddf4c657e5114458cfae75d5e4e6ad6d7 | |
| parent | b3be457e5854e3095cd0be850058c765aaf467ab [diff] |
clk: mediatek: Fix calculation of PLL rate settings Avoid u32 overflow when calculate post divider setting, and increase the max post divider setting from 3 (/8) to 4 (/16). Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>