tree 6e38d880b05897fb97d698a670732b1d474e7e5d
parent a672e99b129e286df2e2697a1b603d82321117f3
author Catalin Marinas <catalin.marinas@arm.com> 1284656237 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1284715012 +0100

ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: <stable@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>