tree e6f09f57843175cca1f3d91593601162bc7454ba
parent d89f2071461d5682b897c73278daaf25fd11aff5
author Damien Lespiau <damien.lespiau@intel.com> 1368190911 +0100
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1368215811 +0200

drm/i915: Compute WR PLL dividers dynamically

Up to now, we were using a static table to match the clock frequency
with a (r2,n2,p) triplet. Despite this table being big, it's by no mean
comprehensive and we had to fall back to the closest frequency when the
requested TMDS clock wasn't in the table.

This patch computes (r2,n2,p) dynamically and get rid of The Big Table.

v2: Replace the floating point constant 1e6 by 1000000

Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=58497
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
[danvet: s/        /^T/]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>