msm: kgsl: Check if GX is on before adding regs
The GMU GX registers require the GX domain to be
on in order to be read. Separate these registers
from the rest of the GMU registers in snapshot
and only add them after checking if GX is on.
CRs-Fixed: 2062271
Change-Id: Ib5db9f81ed39757d23510edb4ad93f910c14a4dc
Signed-off-by: George Shen <sqiao@codeaurora.org>
diff --git a/drivers/gpu/msm/adreno_a6xx_snapshot.c b/drivers/gpu/msm/adreno_a6xx_snapshot.c
index ed0129f..1f97888 100644
--- a/drivers/gpu/msm/adreno_a6xx_snapshot.c
+++ b/drivers/gpu/msm/adreno_a6xx_snapshot.c
@@ -205,13 +205,16 @@
0x3410, 0x3410, 0x3800, 0x3801,
};
-static const unsigned int a6xx_gmu_registers[] = {
+static const unsigned int a6xx_gmu_gx_registers[] = {
/* GMU GX */
0x1A800, 0x1A800, 0x1A810, 0x1A813, 0x1A816, 0x1A816, 0x1A818, 0x1A81B,
0x1A81E, 0x1A81E, 0x1A820, 0x1A823, 0x1A826, 0x1A826, 0x1A828, 0x1A82B,
0x1A82E, 0x1A82E, 0x1A830, 0x1A833, 0x1A836, 0x1A836, 0x1A838, 0x1A83B,
0x1A83E, 0x1A83E, 0x1A840, 0x1A843, 0x1A846, 0x1A846, 0x1A880, 0x1A884,
0x1A900, 0x1A92B, 0x1A940, 0x1A940,
+};
+
+static const unsigned int a6xx_gmu_registers[] = {
/* GMU TCM */
0x1B400, 0x1C3FF, 0x1C400, 0x1D3FF,
/* GMU CX */
@@ -1321,11 +1324,19 @@
static void a6xx_snapshot_gmu(struct kgsl_device *device,
struct kgsl_snapshot *snapshot)
{
+ struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
+ struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
+
if (!kgsl_gmu_isenabled(device))
return;
adreno_snapshot_registers(device, snapshot, a6xx_gmu_registers,
ARRAY_SIZE(a6xx_gmu_registers) / 2);
+
+ if (gpudev->gx_is_on(adreno_dev))
+ adreno_snapshot_registers(device, snapshot,
+ a6xx_gmu_gx_registers,
+ ARRAY_SIZE(a6xx_gmu_gx_registers) / 2);
}
/* a6xx_snapshot_sqe() - Dump SQE data in snapshot */