tree 1f678837f594c5c31cbe0d3f03b09d08f056984e
parent 56c0a94bec625c48fd57e36e4cb693cb684ed76c
author Shashank Babu Chinta Venkata <sbchin@codeaurora.org> 1494279580 -0700
committer Aravind Venkateswaran <aravindh@codeaurora.org> 1494393039 -0700

msm: clk: qcom: fix 10nm DSI PLL set rate sequence

With the current implementation, re-enabling the PLL with
the same rate could result in the VCO not getting configured
correctly. In addition, certain PLL dividers may not be set
with the correct value. Fix this by correcting the XO clock
name to bi_tcxo and caching the pll dividers and restoring
them whenever PLL is re-enabled with the same rate.

Change-Id: If582e4bd37e78298d8f726ad84c9b729d32bec53
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>