Merge "soc: qcom: llcc: Update the active/deactive status check" into msm-4.8
diff --git a/Documentation/devicetree/bindings/fb/mdss-pll.txt b/Documentation/devicetree/bindings/fb/mdss-pll.txt
new file mode 100644
index 0000000..230aef3
--- /dev/null
+++ b/Documentation/devicetree/bindings/fb/mdss-pll.txt
@@ -0,0 +1,88 @@
+Qualcomm Technologies MDSS pll for DSI/EDP/HDMI
+
+mdss-pll is a pll controller device which supports pll devices that
+are compatible with MIPI display serial interface specification,
+HDMI and edp.
+
+Required properties:
+- compatible: Compatible name used in the driver
+ "qcom,mdss_dsi_pll_8916", "qcom,mdss_dsi_pll_8939",
+ "qcom,mdss_dsi_pll_8974", "qcom,mdss_dsi_pll_8994",
+ "qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909",
+ "qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994",
+ "qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992",
+ "qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996",
+ "qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2",
+ "qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8",
+ "qcom,mdss_edp_pll_8996_v3", "qcom,mdss_edp_pll_8996_v3_1p8",
+ "qcom,mdss_dsi_pll_8998", "qcom,mdss_dp_pll_8998",
+ "qcom,mdss_hdmi_pll_8998"
+- cell-index: Specifies the controller used
+- reg: offset and length of the register set for the device.
+- reg-names : names to refer to register sets related to this device
+- gdsc-supply: Phandle for gdsc regulator device node.
+- vddio-supply: Phandle for vddio regulator device node.
+- clocks: List of Phandles for clock device nodes
+ needed by the device.
+- clock-names: List of clock names needed by the device.
+- clock-rate: List of clock rates in Hz.
+
+Optional properties:
+- label: A string used to describe the driver used.
+- vcca-supply: Phandle for vcca regulator device node.
+
+- qcom,platform-supply-entries: A node that lists the elements of the supply. There
+ can be more than one instance of this binding,
+ in which case the entry would be appended with
+ the supply entry index.
+ e.g. qcom,platform-supply-entry@0
+ - reg: offset and length of the register set for the device.
+ -- qcom,supply-name: name of the supply (vdd/vdda/vddio)
+ -- qcom,supply-min-voltage: minimum voltage level (uV)
+ -- qcom,supply-max-voltage: maximum voltage level (uV)
+ -- qcom,supply-enable-load: load drawn (uA) from enabled supply
+ -- qcom,supply-disable-load: load drawn (uA) from disabled supply
+ -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
+ -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
+ -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
+ -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
+
+Example:
+ mdss_dsi0_pll: qcom,mdss_dsi_pll@fd922A00 {
+ compatible = "qcom,mdss_dsi_pll_8974";
+ label = "MDSS DSI 0 PLL";
+ cell-index = <0>;
+
+ reg = <0xfd922A00 0xD4>,
+ <0xfd922900 0x64>,
+ <0xfd8c2300 0x8>;
+ reg-names = "pll_base", "dynamic_pll_base", "gdsc_base";
+ gdsc-supply = <&gdsc_mdss>;
+ vddio-supply = <&pm8941_l12>;
+ vcca-supply = <&pm8941_l28>;
+
+ clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>,
+ <&clock_gcc clk_gcc_mdss_ahb_clk>,
+ <&clock_gcc clk_gcc_mdss_axi_clk>;
+ clock-names = "mdp_core_clk", "iface_clk", "bus_clk";
+ clock-rate = <0>, <0>, <0>;
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-pre-on-sleep = <0>;
+ qcom,supply-post-on-sleep = <20>;
+ qcom,supply-pre-off-sleep = <0>;
+ qcom,supply-post-off-sleep = <0>;
+ };
+ };
+ };
+
diff --git a/Documentation/devicetree/bindings/regulator/proxy-consumer.txt b/Documentation/devicetree/bindings/regulator/proxy-consumer.txt
new file mode 100644
index 0000000..c3fddd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/proxy-consumer.txt
@@ -0,0 +1,32 @@
+Regulator Proxy Consumer Bindings
+
+Regulator proxy consumers provide a means to use a default regulator state
+during bootup only which is removed at the end of boot. This feature can be
+used in situations where a shared regulator can be scaled between several
+possible voltages and hardware requires that it be at a high level at the
+beginning of boot before the consumer device responsible for requesting the
+high level has probed.
+
+Optional properties:
+proxy-supply: phandle of the regulator's own device node.
+ This property is required if any of the three
+ properties below are specified.
+qcom,proxy-consumer-enable: Boolean indicating that the regulator must be
+ kept enabled during boot.
+qcom,proxy-consumer-voltage: List of two integers corresponding the minimum
+ and maximum voltage allowed during boot in
+ microvolts.
+qcom,proxy-consumer-current: Minimum current in microamps required during
+ boot.
+
+Example:
+
+ foo_vreg: regulator@0 {
+ regulator-name = "foo";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <2000000>;
+ proxy-supply = <&foo_vreg>;
+ qcom,proxy-consumer-voltage = <1500000 2000000>;
+ qcom,proxy-consumer-current = <25000>;
+ qcom,proxy-consumer-enable;
+ };
diff --git a/arch/arm64/configs/msmskunk-perf_defconfig b/arch/arm64/configs/msmskunk-perf_defconfig
index 8136df2..dd62a315 100644
--- a/arch/arm64/configs/msmskunk-perf_defconfig
+++ b/arch/arm64/configs/msmskunk-perf_defconfig
@@ -12,6 +12,8 @@
CONFIG_RT_GROUP_SCHED=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_CPUACCT=y
+CONFIG_SCHED_HMP=y
+CONFIG_SCHED_HMP_CSTATE_AWARE=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
diff --git a/arch/arm64/configs/msmskunk_defconfig b/arch/arm64/configs/msmskunk_defconfig
index 8b75628..01a72b8 100644
--- a/arch/arm64/configs/msmskunk_defconfig
+++ b/arch/arm64/configs/msmskunk_defconfig
@@ -13,6 +13,8 @@
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_DEBUG=y
+CONFIG_SCHED_HMP=y
+CONFIG_SCHED_HMP_CSTATE_AWARE=y
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_PID_NS is not set
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 163c5f2..5fc1112 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -41,6 +41,7 @@
#include <asm/pgtable.h>
#include <asm/tlbflush.h>
#include <asm/kryo3xx-arm64-edac.h>
+#include <soc/qcom/scm.h>
static const char *fault_name(unsigned int esr);
@@ -445,6 +446,23 @@
return 0;
}
+static int do_tlb_conf_fault(unsigned long addr,
+ unsigned int esr,
+ struct pt_regs *regs)
+{
+#define SCM_TLB_CONFLICT_CMD 0x1B
+ struct scm_desc desc = {
+ .args[0] = addr,
+ .arginfo = SCM_ARGS(1),
+ };
+
+ if (scm_call2_atomic(SCM_SIP_FNID(SCM_SVC_MP, SCM_TLB_CONFLICT_CMD),
+ &desc))
+ return 1;
+
+ return 0;
+}
+
/*
* First Level Translation Fault Handler
*
@@ -543,7 +561,7 @@
{ do_bad, SIGBUS, 0, "unknown 45" },
{ do_bad, SIGBUS, 0, "unknown 46" },
{ do_bad, SIGBUS, 0, "unknown 47" },
- { do_bad, SIGBUS, 0, "TLB conflict abort" },
+ { do_tlb_conf_fault, SIGBUS, 0, "TLB conflict abort" },
{ do_bad, SIGBUS, 0, "unknown 49" },
{ do_bad, SIGBUS, 0, "unknown 50" },
{ do_bad, SIGBUS, 0, "unknown 51" },
diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
index 4c28e1a..08f512b 100644
--- a/drivers/base/cpu.c
+++ b/drivers/base/cpu.c
@@ -180,10 +180,105 @@
};
#endif
+#ifdef CONFIG_SCHED_HMP
+
+static ssize_t show_sched_static_cpu_pwr_cost(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct cpu *cpu = container_of(dev, struct cpu, dev);
+ ssize_t rc;
+ int cpuid = cpu->dev.id;
+ unsigned int pwr_cost;
+
+ pwr_cost = sched_get_static_cpu_pwr_cost(cpuid);
+
+ rc = snprintf(buf, PAGE_SIZE-2, "%d\n", pwr_cost);
+
+ return rc;
+}
+
+static ssize_t __ref store_sched_static_cpu_pwr_cost(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct cpu *cpu = container_of(dev, struct cpu, dev);
+ int err;
+ int cpuid = cpu->dev.id;
+ unsigned int pwr_cost;
+
+ err = kstrtouint(strstrip((char *)buf), 0, &pwr_cost);
+ if (err)
+ return err;
+
+ err = sched_set_static_cpu_pwr_cost(cpuid, pwr_cost);
+
+ if (err >= 0)
+ err = count;
+
+ return err;
+}
+
+static ssize_t show_sched_static_cluster_pwr_cost(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct cpu *cpu = container_of(dev, struct cpu, dev);
+ ssize_t rc;
+ int cpuid = cpu->dev.id;
+ unsigned int pwr_cost;
+
+ pwr_cost = sched_get_static_cluster_pwr_cost(cpuid);
+
+ rc = snprintf(buf, PAGE_SIZE-2, "%d\n", pwr_cost);
+
+ return rc;
+}
+
+static ssize_t __ref store_sched_static_cluster_pwr_cost(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct cpu *cpu = container_of(dev, struct cpu, dev);
+ int err;
+ int cpuid = cpu->dev.id;
+ unsigned int pwr_cost;
+
+ err = kstrtouint(strstrip((char *)buf), 0, &pwr_cost);
+ if (err)
+ return err;
+
+ err = sched_set_static_cluster_pwr_cost(cpuid, pwr_cost);
+
+ if (err >= 0)
+ err = count;
+
+ return err;
+}
+
+static DEVICE_ATTR(sched_static_cpu_pwr_cost, 0644,
+ show_sched_static_cpu_pwr_cost,
+ store_sched_static_cpu_pwr_cost);
+static DEVICE_ATTR(sched_static_cluster_pwr_cost, 0644,
+ show_sched_static_cluster_pwr_cost,
+ store_sched_static_cluster_pwr_cost);
+
+static struct attribute *hmp_sched_cpu_attrs[] = {
+ &dev_attr_sched_static_cpu_pwr_cost.attr,
+ &dev_attr_sched_static_cluster_pwr_cost.attr,
+ NULL
+};
+
+static struct attribute_group sched_hmp_cpu_attr_group = {
+ .attrs = hmp_sched_cpu_attrs,
+};
+
+#endif /* CONFIG_SCHED_HMP */
static const struct attribute_group *common_cpu_attr_groups[] = {
#ifdef CONFIG_KEXEC
&crash_note_cpu_attr_group,
#endif
+#ifdef CONFIG_SCHED_HMP
+ &sched_hmp_cpu_attr_group,
+#endif
NULL
};
@@ -191,6 +286,9 @@
#ifdef CONFIG_KEXEC
&crash_note_cpu_attr_group,
#endif
+#ifdef CONFIG_SCHED_HMP
+ &sched_hmp_cpu_attr_group,
+#endif
NULL
};
diff --git a/drivers/clk/qcom/mdss/Kconfig b/drivers/clk/qcom/mdss/Kconfig
new file mode 100644
index 0000000..229780e
--- /dev/null
+++ b/drivers/clk/qcom/mdss/Kconfig
@@ -0,0 +1,6 @@
+config MSM_MDSS_PLL
+ bool "MDSS pll programming"
+ ---help---
+ It provides support for DSI, eDP and HDMI interface pll programming on MDSS
+ hardware. It also handles the pll specific resources and turn them on/off when
+ mdss pll client tries to enable/disable pll clocks.
diff --git a/drivers/clk/qcom/mdss/Makefile b/drivers/clk/qcom/mdss/Makefile
new file mode 100644
index 0000000..373cf45
--- /dev/null
+++ b/drivers/clk/qcom/mdss/Makefile
@@ -0,0 +1,9 @@
+obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll-util.o
+obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll.o
+obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-util.o mdss-dsi-20nm-pll-util.o
+obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28hpm.o
+obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-28lpm.o
+obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-20nm.o
+obj-$(CONFIG_MSM_MDSS_PLL) += mdss-edp-pll-28hpm.o
+obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-28hpm.o
+obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-20nm.o
diff --git a/drivers/clk/qcom/mdss/mdss-dsi-20nm-pll-util.c b/drivers/clk/qcom/mdss/mdss-dsi-20nm-pll-util.c
new file mode 100644
index 0000000..fa917a8
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-dsi-20nm-pll-util.c
@@ -0,0 +1,956 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <linux/delay.h>
+#include <linux/clk/msm-clock-generic.h>
+
+#include "mdss-pll.h"
+#include "mdss-dsi-pll.h"
+
+#define MMSS_DSI_PHY_PLL_SYS_CLK_CTRL 0x0000
+#define MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN 0x0004
+#define MMSS_DSI_PHY_PLL_CMN_MODE 0x0008
+#define MMSS_DSI_PHY_PLL_IE_TRIM 0x000C
+#define MMSS_DSI_PHY_PLL_IP_TRIM 0x0010
+
+#define MMSS_DSI_PHY_PLL_PLL_PHSEL_CONTROL 0x0018
+#define MMSS_DSI_PHY_PLL_IPTAT_TRIM_VCCA_TX_SEL 0x001C
+#define MMSS_DSI_PHY_PLL_PLL_PHSEL_DC 0x0020
+#define MMSS_DSI_PHY_PLL_PLL_IP_SETI 0x0024
+#define MMSS_DSI_PHY_PLL_CORE_CLK_IN_SYNC_SEL 0x0028
+
+#define MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN 0x0030
+#define MMSS_DSI_PHY_PLL_PLL_CP_SETI 0x0034
+#define MMSS_DSI_PHY_PLL_PLL_IP_SETP 0x0038
+#define MMSS_DSI_PHY_PLL_PLL_CP_SETP 0x003C
+#define MMSS_DSI_PHY_PLL_ATB_SEL1 0x0040
+#define MMSS_DSI_PHY_PLL_ATB_SEL2 0x0044
+#define MMSS_DSI_PHY_PLL_SYSCLK_EN_SEL_TXBAND 0x0048
+#define MMSS_DSI_PHY_PLL_RESETSM_CNTRL 0x004C
+#define MMSS_DSI_PHY_PLL_RESETSM_CNTRL2 0x0050
+#define MMSS_DSI_PHY_PLL_RESETSM_CNTRL3 0x0054
+#define MMSS_DSI_PHY_PLL_RESETSM_PLL_CAL_COUNT1 0x0058
+#define MMSS_DSI_PHY_PLL_RESETSM_PLL_CAL_COUNT2 0x005C
+#define MMSS_DSI_PHY_PLL_DIV_REF1 0x0060
+#define MMSS_DSI_PHY_PLL_DIV_REF2 0x0064
+#define MMSS_DSI_PHY_PLL_KVCO_COUNT1 0x0068
+#define MMSS_DSI_PHY_PLL_KVCO_COUNT2 0x006C
+#define MMSS_DSI_PHY_PLL_KVCO_CAL_CNTRL 0x0070
+#define MMSS_DSI_PHY_PLL_KVCO_CODE 0x0074
+#define MMSS_DSI_PHY_PLL_VREF_CFG1 0x0078
+#define MMSS_DSI_PHY_PLL_VREF_CFG2 0x007C
+#define MMSS_DSI_PHY_PLL_VREF_CFG3 0x0080
+#define MMSS_DSI_PHY_PLL_VREF_CFG4 0x0084
+#define MMSS_DSI_PHY_PLL_VREF_CFG5 0x0088
+#define MMSS_DSI_PHY_PLL_VREF_CFG6 0x008C
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP1 0x0090
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP2 0x0094
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP3 0x0098
+
+#define MMSS_DSI_PHY_PLL_BGTC 0x00A0
+#define MMSS_DSI_PHY_PLL_PLL_TEST_UPDN 0x00A4
+#define MMSS_DSI_PHY_PLL_PLL_VCO_TUNE 0x00A8
+#define MMSS_DSI_PHY_PLL_DEC_START1 0x00AC
+#define MMSS_DSI_PHY_PLL_PLL_AMP_OS 0x00B0
+#define MMSS_DSI_PHY_PLL_SSC_EN_CENTER 0x00B4
+#define MMSS_DSI_PHY_PLL_SSC_ADJ_PER1 0x00B8
+#define MMSS_DSI_PHY_PLL_SSC_ADJ_PER2 0x00BC
+#define MMSS_DSI_PHY_PLL_SSC_PER1 0x00C0
+#define MMSS_DSI_PHY_PLL_SSC_PER2 0x00C4
+#define MMSS_DSI_PHY_PLL_SSC_STEP_SIZE1 0x00C8
+#define MMSS_DSI_PHY_PLL_SSC_STEP_SIZE2 0x00CC
+#define MMSS_DSI_PHY_PLL_RES_CODE_UP 0x00D0
+#define MMSS_DSI_PHY_PLL_RES_CODE_DN 0x00D4
+#define MMSS_DSI_PHY_PLL_RES_CODE_UP_OFFSET 0x00D8
+#define MMSS_DSI_PHY_PLL_RES_CODE_DN_OFFSET 0x00DC
+#define MMSS_DSI_PHY_PLL_RES_CODE_START_SEG1 0x00E0
+#define MMSS_DSI_PHY_PLL_RES_CODE_START_SEG2 0x00E4
+#define MMSS_DSI_PHY_PLL_RES_CODE_CAL_CSR 0x00E8
+#define MMSS_DSI_PHY_PLL_RES_CODE 0x00EC
+#define MMSS_DSI_PHY_PLL_RES_TRIM_CONTROL 0x00F0
+#define MMSS_DSI_PHY_PLL_RES_TRIM_CONTROL2 0x00F4
+#define MMSS_DSI_PHY_PLL_RES_TRIM_EN_VCOCALDONE 0x00F8
+#define MMSS_DSI_PHY_PLL_FAUX_EN 0x00FC
+
+#define MMSS_DSI_PHY_PLL_DIV_FRAC_START1 0x0100
+#define MMSS_DSI_PHY_PLL_DIV_FRAC_START2 0x0104
+#define MMSS_DSI_PHY_PLL_DIV_FRAC_START3 0x0108
+#define MMSS_DSI_PHY_PLL_DEC_START2 0x010C
+#define MMSS_DSI_PHY_PLL_PLL_RXTXEPCLK_EN 0x0110
+#define MMSS_DSI_PHY_PLL_PLL_CRCTRL 0x0114
+#define MMSS_DSI_PHY_PLL_LOW_POWER_RO_CONTROL 0x013C
+#define MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL 0x0140
+#define MMSS_DSI_PHY_PLL_HR_OCLK2_DIVIDER 0x0144
+#define MMSS_DSI_PHY_PLL_HR_OCLK3_DIVIDER 0x0148
+#define MMSS_DSI_PHY_PLL_PLL_VCO_HIGH 0x014C
+#define MMSS_DSI_PHY_PLL_RESET_SM 0x0150
+#define MMSS_DSI_PHY_PLL_MUXVAL 0x0154
+#define MMSS_DSI_PHY_PLL_CORE_RES_CODE_DN 0x0158
+#define MMSS_DSI_PHY_PLL_CORE_RES_CODE_UP 0x015C
+#define MMSS_DSI_PHY_PLL_CORE_VCO_TUNE 0x0160
+#define MMSS_DSI_PHY_PLL_CORE_VCO_TAIL 0x0164
+#define MMSS_DSI_PHY_PLL_CORE_KVCO_CODE 0x0168
+
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL0 0x014
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL1 0x018
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL2 0x01C
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL3 0x020
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL4 0x024
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL5 0x028
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL6 0x02C
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL7 0x030
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL8 0x034
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL9 0x038
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL10 0x03C
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL11 0x040
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL12 0x044
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL13 0x048
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL14 0x04C
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL15 0x050
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL16 0x054
+#define MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL17 0x058
+
+#define DSI_PLL_POLL_MAX_READS 15
+#define DSI_PLL_POLL_TIMEOUT_US 1000
+
+int set_mdss_byte_mux_sel(struct mux_clk *clk, int sel)
+{
+ return 0;
+}
+
+int get_mdss_byte_mux_sel(struct mux_clk *clk)
+{
+ return 0;
+}
+
+int set_mdss_pixel_mux_sel(struct mux_clk *clk, int sel)
+{
+ return 0;
+}
+
+int get_mdss_pixel_mux_sel(struct mux_clk *clk)
+{
+ return 0;
+}
+
+static void pll_20nm_cache_trim_codes(struct mdss_pll_resources *dsi_pll_res)
+{
+ int rc;
+
+ if (dsi_pll_res->reg_upd)
+ return;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return;
+ }
+
+ dsi_pll_res->cache_pll_trim_codes[0] =
+ MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_CORE_KVCO_CODE);
+ dsi_pll_res->cache_pll_trim_codes[1] =
+ MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_CORE_VCO_TUNE);
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+
+ dsi_pll_res->reg_upd = true;
+}
+
+static void pll_20nm_override_trim_codes(struct mdss_pll_resources *dsi_pll_res)
+{
+ u32 reg_data;
+ void __iomem *pll_base = dsi_pll_res->pll_base;
+
+ /*
+ * Override mux config for all cached trim codes from
+ * saved config except for VCO Tune
+ */
+ reg_data = (dsi_pll_res->cache_pll_trim_codes[0] & 0x3f) | BIT(5);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_KVCO_CODE, reg_data);
+
+ reg_data = (dsi_pll_res->cache_pll_trim_codes[1] & 0x7f) | BIT(7);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_VCO_TUNE, reg_data);
+}
+
+
+int set_bypass_lp_div_mux_sel(struct mux_clk *clk, int sel)
+{
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+ int reg_data;
+
+ pr_debug("bypass_lp_div mux set to %s mode\n",
+ sel ? "indirect" : "direct");
+
+ pr_debug("POST_DIVIDER_CONTROL = 0x%x\n",
+ MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL));
+
+ reg_data = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL);
+ reg_data |= BIT(7);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL,
+ reg_data | (sel << 5));
+ pr_debug("POST_DIVIDER_CONTROL = 0x%x\n",
+ MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL));
+
+ return 0;
+}
+
+int set_shadow_bypass_lp_div_mux_sel(struct mux_clk *clk, int sel)
+{
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+ int reg_data, rem;
+
+ if (!dsi_pll_res->resource_enable) {
+ pr_err("PLL resources disabled. Dynamic fps invalid\n");
+ return -EINVAL;
+ }
+
+ reg_data = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL);
+ reg_data |= BIT(7);
+
+ pr_debug("%d: reg_data = %x\n", __LINE__, reg_data);
+
+ /* Repeat POST DIVIDER 2 times (4 writes)*/
+ for (rem = 0; rem < 2; rem++)
+ MDSS_DYN_PLL_REG_W(dsi_pll_res->dyn_pll_base,
+ MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL16 + (4 * rem),
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL,
+ (reg_data | (sel << 5)), (reg_data | (sel << 5)));
+
+ return 0;
+}
+
+int get_bypass_lp_div_mux_sel(struct mux_clk *clk)
+{
+ int mux_mode, rc;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ if (is_gdsc_disabled(dsi_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ mux_mode = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL) & BIT(5);
+
+ pr_debug("bypass_lp_div mux mode = %s",
+ mux_mode ? "indirect" : "direct");
+ mdss_pll_resource_enable(dsi_pll_res, false);
+
+ return !!mux_mode;
+}
+
+int ndiv_set_div(struct div_clk *clk, int div)
+{
+ int rc, reg_data;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ reg_data = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL,
+ reg_data | div);
+
+ pr_debug("POST_DIVIDER_CONTROL = 0x%x\n",
+ MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL));
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return rc;
+}
+
+int shadow_ndiv_set_div(struct div_clk *clk, int div)
+{
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ if (!dsi_pll_res->resource_enable) {
+ pr_err("PLL resources disabled. Dynamic fps invalid\n");
+ return -EINVAL;
+ }
+
+ pr_debug("%d div=%i\n", __LINE__, div);
+
+ MDSS_DYN_PLL_REG_W(dsi_pll_res->dyn_pll_base,
+ MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL14,
+ MMSS_DSI_PHY_PLL_RESETSM_CNTRL3,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL,
+ 0x07, (0xB | div));
+
+ return 0;
+}
+
+int ndiv_get_div(struct div_clk *clk)
+{
+ int div = 0, rc;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ if (is_gdsc_disabled(dsi_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(clk->priv, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ div = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL) & 0x0F;
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+
+ return div;
+}
+
+int fixed_hr_oclk2_set_div(struct div_clk *clk, int div)
+{
+ int rc;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_HR_OCLK2_DIVIDER,
+ (div - 1));
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return rc;
+}
+
+int shadow_fixed_hr_oclk2_set_div(struct div_clk *clk, int div)
+{
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ if (!dsi_pll_res->resource_enable) {
+ pr_err("PLL resources disabled. Dynamic fps invalid\n");
+ return -EINVAL;
+ }
+ pr_debug("%d div = %d\n", __LINE__, div);
+
+ MDSS_DYN_PLL_REG_W(dsi_pll_res->dyn_pll_base,
+ MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL5,
+ MMSS_DSI_PHY_PLL_HR_OCLK2_DIVIDER,
+ MMSS_DSI_PHY_PLL_HR_OCLK2_DIVIDER,
+ (div - 1), (div - 1));
+
+ return 0;
+}
+
+int fixed_hr_oclk2_get_div(struct div_clk *clk)
+{
+ int div = 0, rc;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ if (is_gdsc_disabled(dsi_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ div = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_HR_OCLK2_DIVIDER);
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return div + 1;
+}
+
+int hr_oclk3_set_div(struct div_clk *clk, int div)
+{
+ int rc;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ pr_debug("%d div = %d\n", __LINE__, div);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_HR_OCLK3_DIVIDER,
+ (div - 1));
+ pr_debug("%s: HR_OCLK3_DIVIDER = 0x%x\n", __func__,
+ MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_HR_OCLK3_DIVIDER));
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return rc;
+}
+
+int shadow_hr_oclk3_set_div(struct div_clk *clk, int div)
+{
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ if (!dsi_pll_res->resource_enable) {
+ pr_err("PLL resources disabled. Dynamic fps invalid\n");
+ return -EINVAL;
+ }
+
+ pr_debug("%d div = %d\n", __LINE__, div);
+
+ MDSS_DYN_PLL_REG_W(dsi_pll_res->dyn_pll_base,
+ MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL6,
+ MMSS_DSI_PHY_PLL_HR_OCLK3_DIVIDER,
+ MMSS_DSI_PHY_PLL_HR_OCLK3_DIVIDER,
+ (div - 1), (div - 1));
+
+ return 0;
+}
+
+int hr_oclk3_get_div(struct div_clk *clk)
+{
+ int div = 0, rc;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ if (is_gdsc_disabled(dsi_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ div = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_HR_OCLK3_DIVIDER);
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return div + 1;
+}
+
+static bool pll_20nm_is_pll_locked(struct mdss_pll_resources *dsi_pll_res)
+{
+ u32 status;
+ bool pll_locked;
+
+ /* poll for PLL ready status */
+ if (readl_poll_timeout_atomic((dsi_pll_res->pll_base +
+ MMSS_DSI_PHY_PLL_RESET_SM),
+ status,
+ ((status & BIT(5)) > 0),
+ DSI_PLL_POLL_MAX_READS,
+ DSI_PLL_POLL_TIMEOUT_US)) {
+ pr_debug("DSI PLL status=%x failed to Lock\n", status);
+ pll_locked = false;
+ } else if (readl_poll_timeout_atomic((dsi_pll_res->pll_base +
+ MMSS_DSI_PHY_PLL_RESET_SM),
+ status,
+ ((status & BIT(6)) > 0),
+ DSI_PLL_POLL_MAX_READS,
+ DSI_PLL_POLL_TIMEOUT_US)) {
+ pr_debug("DSI PLL status=%x PLl not ready\n", status);
+ pll_locked = false;
+ } else {
+ pll_locked = true;
+ }
+
+ return pll_locked;
+}
+
+void __dsi_pll_disable(void __iomem *pll_base)
+{
+ if (!pll_base) {
+ pr_err("Invalid pll base\n");
+ return;
+ }
+ pr_debug("Disabling PHY PLL for PLL_BASE=%p\n", pll_base);
+
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN, 0x02);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_RESETSM_CNTRL3, 0x06);
+}
+
+static int dsi_pll_enable(struct clk *c)
+{
+ int i, rc;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ /* Try all enable sequences until one succeeds */
+ for (i = 0; i < vco->pll_en_seq_cnt; i++) {
+ rc = vco->pll_enable_seqs[i](dsi_pll_res);
+ pr_debug("DSI PLL %s after sequence #%d\n",
+ rc ? "unlocked" : "locked", i + 1);
+ if (!rc)
+ break;
+ }
+ /* Disable PLL1 to avoid current leakage while toggling MDSS GDSC */
+ if (dsi_pll_res->pll_1_base)
+ __dsi_pll_disable(dsi_pll_res->pll_1_base);
+
+ if (rc) {
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ pr_err("DSI PLL failed to lock\n");
+ }
+ dsi_pll_res->pll_on = true;
+
+ return rc;
+}
+
+
+static void pll_20nm_config_powerdown(void __iomem *pll_base)
+{
+ if (!pll_base) {
+ pr_err("Invalid pll base.\n");
+ return;
+ }
+
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_SYS_CLK_CTRL, 0x00);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_CMN_MODE, 0x01);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN, 0x82);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN, 0x02);
+}
+
+static void dsi_pll_disable(struct clk *c)
+{
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ if (!dsi_pll_res->pll_on &&
+ mdss_pll_resource_enable(dsi_pll_res, true)) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return;
+ }
+
+ dsi_pll_res->handoff_resources = false;
+
+ __dsi_pll_disable(dsi_pll_res->pll_base);
+
+ /* Disable PLL1 to avoid current leakage while toggling MDSS GDSC */
+ if (dsi_pll_res->pll_1_base)
+ __dsi_pll_disable(dsi_pll_res->pll_1_base);
+
+ pll_20nm_config_powerdown(dsi_pll_res->pll_base);
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+
+ dsi_pll_res->pll_on = false;
+
+ pr_debug("DSI PLL Disabled\n");
+}
+
+static void pll_20nm_config_common_block(void __iomem *pll_base)
+{
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN, 0x82);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN, 0x2a);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN, 0x2b);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_RESETSM_CNTRL3, 0x02);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_SYS_CLK_CTRL, 0x40);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_IE_TRIM, 0x0F);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_IP_TRIM, 0x0F);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_PHSEL_CONTROL, 0x08);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_IPTAT_TRIM_VCCA_TX_SEL, 0x0E);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN, 0x08);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_SYSCLK_EN_SEL_TXBAND, 0x4A);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_DIV_REF1, 0x00);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_DIV_REF2, 0x01);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_CNTRL, 0x07);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_KVCO_CAL_CNTRL, 0x1f);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_KVCO_COUNT1, 0x8A);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_VREF_CFG3, 0x10);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_SSC_EN_CENTER, 0x00);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_FAUX_EN, 0x0C);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_RXTXEPCLK_EN, 0x0a);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_LOW_POWER_RO_CONTROL, 0x0f);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_CMN_MODE, 0x00);
+}
+
+static void pll_20nm_config_loop_bw(void __iomem *pll_base)
+{
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_IP_SETI, 0x03);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_CP_SETI, 0x3F);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_IP_SETP, 0x03);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_CP_SETP, 0x1F);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_CRCTRL, 0x77);
+}
+
+static void pll_20nm_vco_rate_calc(struct mdss_pll_vco_calc *vco_calc,
+ s64 vco_clk_rate, s64 ref_clk_rate)
+{
+ s64 multiplier = (1 << 20);
+ s64 duration = 1024, pll_comp_val;
+ s64 dec_start_multiple, dec_start;
+ s32 div_frac_start;
+ s64 dec_start1, dec_start2;
+ s32 div_frac_start1, div_frac_start2, div_frac_start3;
+ s64 pll_plllock_cmp1, pll_plllock_cmp2, pll_plllock_cmp3;
+
+ memset(vco_calc, 0, sizeof(*vco_calc));
+ pr_debug("vco_clk_rate=%lld ref_clk_rate=%lld\n", vco_clk_rate,
+ ref_clk_rate);
+
+ dec_start_multiple = div_s64(vco_clk_rate * multiplier,
+ 2 * ref_clk_rate);
+ div_s64_rem(dec_start_multiple,
+ multiplier, &div_frac_start);
+
+ dec_start = div_s64(dec_start_multiple, multiplier);
+ dec_start1 = (dec_start & 0x7f) | BIT(7);
+ dec_start2 = ((dec_start & 0x80) >> 7) | BIT(1);
+ div_frac_start1 = (div_frac_start & 0x7f) | BIT(7);
+ div_frac_start2 = ((div_frac_start >> 7) & 0x7f) | BIT(7);
+ div_frac_start3 = ((div_frac_start >> 14) & 0x3f) | BIT(6);
+ pll_comp_val = (div_s64(dec_start_multiple * 2 * duration,
+ 10 * multiplier)) - 1;
+ pll_plllock_cmp1 = pll_comp_val & 0xff;
+ pll_plllock_cmp2 = (pll_comp_val >> 8) & 0xff;
+ pll_plllock_cmp3 = (pll_comp_val >> 16) & 0xff;
+
+ pr_debug("dec_start_multiple = 0x%llx\n", dec_start_multiple);
+ pr_debug("dec_start = 0x%llx, div_frac_start = 0x%x\n",
+ dec_start, div_frac_start);
+ pr_debug("dec_start1 = 0x%llx, dec_start2 = 0x%llx\n",
+ dec_start1, dec_start2);
+ pr_debug("div_frac_start1 = 0x%x, div_frac_start2 = 0x%x\n",
+ div_frac_start1, div_frac_start2);
+ pr_debug("div_frac_start3 = 0x%x\n", div_frac_start3);
+ pr_debug("pll_comp_val = 0x%llx\n", pll_comp_val);
+ pr_debug("pll_plllock_cmp1 = 0x%llx, pll_plllock_cmp2 =%llx\n",
+ pll_plllock_cmp1, pll_plllock_cmp2);
+ pr_debug("pll_plllock_cmp3 = 0x%llx\n", pll_plllock_cmp3);
+
+ /* Assign to vco struct */
+ vco_calc->div_frac_start1 = div_frac_start1;
+ vco_calc->div_frac_start2 = div_frac_start2;
+ vco_calc->div_frac_start3 = div_frac_start3;
+ vco_calc->dec_start1 = dec_start1;
+ vco_calc->dec_start2 = dec_start2;
+ vco_calc->pll_plllock_cmp1 = pll_plllock_cmp1;
+ vco_calc->pll_plllock_cmp2 = pll_plllock_cmp2;
+ vco_calc->pll_plllock_cmp3 = pll_plllock_cmp3;
+}
+
+static void pll_20nm_config_vco_rate(void __iomem *pll_base,
+ struct mdss_pll_vco_calc *vco_calc)
+{
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_DIV_FRAC_START1,
+ vco_calc->div_frac_start1);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_DIV_FRAC_START2,
+ vco_calc->div_frac_start2);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_DIV_FRAC_START3,
+ vco_calc->div_frac_start3);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_DEC_START1,
+ vco_calc->dec_start1);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_DEC_START2,
+ vco_calc->dec_start2);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLLLOCK_CMP1,
+ vco_calc->pll_plllock_cmp1);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLLLOCK_CMP2,
+ vco_calc->pll_plllock_cmp2);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLLLOCK_CMP3,
+ vco_calc->pll_plllock_cmp3);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN, 0x01);
+}
+
+int pll_20nm_vco_set_rate(struct dsi_pll_vco_clk *vco, unsigned long rate)
+{
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ dsi_pll_res->vco_current_rate = rate;
+ dsi_pll_res->vco_ref_clk_rate = vco->ref_clk_rate;
+
+ return 0;
+}
+
+int shadow_pll_20nm_vco_set_rate(struct dsi_pll_vco_clk *vco,
+ unsigned long rate)
+{
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+ struct mdss_pll_vco_calc vco_calc;
+ s64 vco_clk_rate = rate;
+ u32 rem;
+
+ if (!dsi_pll_res->resource_enable) {
+ pr_err("PLL resources disabled. Dynamic fps invalid\n");
+ return -EINVAL;
+ }
+
+ pr_debug("req vco set rate: %lld\n", vco_clk_rate);
+
+ pll_20nm_override_trim_codes(dsi_pll_res);
+
+ /* div fraction, start and comp calculations */
+ pll_20nm_vco_rate_calc(&vco_calc, vco_clk_rate,
+ dsi_pll_res->vco_ref_clk_rate);
+
+ MDSS_DYN_PLL_REG_W(dsi_pll_res->dyn_pll_base,
+ MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL0,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL,
+ MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN,
+ 0xB1, 0);
+ MDSS_DYN_PLL_REG_W(dsi_pll_res->dyn_pll_base,
+ MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL1,
+ MMSS_DSI_PHY_PLL_PLLLOCK_CMP1,
+ MMSS_DSI_PHY_PLL_PLLLOCK_CMP2,
+ vco_calc.pll_plllock_cmp1, vco_calc.pll_plllock_cmp2);
+ MDSS_DYN_PLL_REG_W(dsi_pll_res->dyn_pll_base,
+ MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL2,
+ MMSS_DSI_PHY_PLL_PLLLOCK_CMP3,
+ MMSS_DSI_PHY_PLL_DEC_START1,
+ vco_calc.pll_plllock_cmp3, vco_calc.dec_start1);
+ MDSS_DYN_PLL_REG_W(dsi_pll_res->dyn_pll_base,
+ MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL3,
+ MMSS_DSI_PHY_PLL_DEC_START2,
+ MMSS_DSI_PHY_PLL_DIV_FRAC_START1,
+ vco_calc.dec_start2, vco_calc.div_frac_start1);
+ MDSS_DYN_PLL_REG_W(dsi_pll_res->dyn_pll_base,
+ MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL4,
+ MMSS_DSI_PHY_PLL_DIV_FRAC_START2,
+ MMSS_DSI_PHY_PLL_DIV_FRAC_START3,
+ vco_calc.div_frac_start2, vco_calc.div_frac_start3);
+ /* Method 2 - Auto PLL calibration */
+ MDSS_DYN_PLL_REG_W(dsi_pll_res->dyn_pll_base,
+ MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL7,
+ MMSS_DSI_PHY_PLL_PLL_VCO_TUNE,
+ MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN,
+ 0, 0x0D);
+ MDSS_DYN_PLL_REG_W(dsi_pll_res->dyn_pll_base,
+ MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL8,
+ MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL,
+ MMSS_DSI_PHY_PLL_RESETSM_CNTRL3,
+ 0xF0, 0x07);
+
+ /*
+ * RESETSM_CTRL3 has to be set for 12 times (6 reg writes),
+ * Each register setting write 2 times, running in loop for 5
+ * times (5 reg writes) and other two iterations are taken
+ * care (one above and other in shadow_bypass
+ */
+ for (rem = 0; rem < 5; rem++) {
+ MDSS_DYN_PLL_REG_W(dsi_pll_res->dyn_pll_base,
+ MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL9 + (4 * rem),
+ MMSS_DSI_PHY_PLL_RESETSM_CNTRL3,
+ MMSS_DSI_PHY_PLL_RESETSM_CNTRL3,
+ 0x07, 0x07);
+ }
+
+ MDSS_DYN_PLL_REG_W(dsi_pll_res->dyn_pll_base,
+ MMSS_DSI_DYNAMIC_REFRESH_PLL_CTRL15,
+ MMSS_DSI_PHY_PLL_RESETSM_CNTRL3,
+ MMSS_DSI_PHY_PLL_RESETSM_CNTRL3,
+ 0x03, 0x03);
+
+ /* memory barrier */
+ wmb();
+ return 0;
+}
+
+unsigned long pll_20nm_vco_get_rate(struct clk *c)
+{
+ u64 vco_rate, multiplier = (1 << 20);
+ s32 div_frac_start;
+ u32 dec_start;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ u64 ref_clk = vco->ref_clk_rate;
+ int rc;
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ if (is_gdsc_disabled(dsi_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ dec_start = (MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_DEC_START2) & BIT(0)) << 7;
+ dec_start |= (MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_DEC_START1) & 0x7f);
+ pr_debug("dec_start = 0x%x\n", dec_start);
+
+ div_frac_start = (MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_DIV_FRAC_START3) & 0x3f) << 14;
+ div_frac_start |= (MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_DIV_FRAC_START2) & 0x7f) << 7;
+ div_frac_start |= MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ MMSS_DSI_PHY_PLL_DIV_FRAC_START1) & 0x7f;
+ pr_debug("div_frac_start = 0x%x\n", div_frac_start);
+
+ vco_rate = ref_clk * 2 * dec_start;
+ vco_rate += ((ref_clk * 2 * div_frac_start) / multiplier);
+ pr_debug("returning vco rate = %lu\n", (unsigned long)vco_rate);
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+
+ return (unsigned long)vco_rate;
+}
+long pll_20nm_vco_round_rate(struct clk *c, unsigned long rate)
+{
+ unsigned long rrate = rate;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+
+ if (rate < vco->min_rate)
+ rrate = vco->min_rate;
+ if (rate > vco->max_rate)
+ rrate = vco->max_rate;
+
+ return rrate;
+}
+
+enum handoff pll_20nm_vco_handoff(struct clk *c)
+{
+ int rc;
+ enum handoff ret = HANDOFF_DISABLED_CLK;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ if (is_gdsc_disabled(dsi_pll_res))
+ return HANDOFF_DISABLED_CLK;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return ret;
+ }
+
+ if (pll_20nm_is_pll_locked(dsi_pll_res)) {
+ dsi_pll_res->handoff_resources = true;
+ dsi_pll_res->pll_on = true;
+ c->rate = pll_20nm_vco_get_rate(c);
+ ret = HANDOFF_ENABLED_CLK;
+ } else {
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ }
+
+ return ret;
+}
+
+int pll_20nm_vco_prepare(struct clk *c)
+{
+ int rc = 0;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ if (!dsi_pll_res) {
+ pr_err("Dsi pll resources are not available\n");
+ return -EINVAL;
+ }
+
+ if ((dsi_pll_res->vco_cached_rate != 0)
+ && (dsi_pll_res->vco_cached_rate == c->rate)) {
+ rc = c->ops->set_rate(c, dsi_pll_res->vco_cached_rate);
+ if (rc) {
+ pr_err("vco_set_rate failed. rc=%d\n", rc);
+ goto error;
+ }
+ }
+
+ rc = dsi_pll_enable(c);
+
+error:
+ return rc;
+}
+
+void pll_20nm_vco_unprepare(struct clk *c)
+{
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ if (!dsi_pll_res) {
+ pr_err("Dsi pll resources are not available\n");
+ return;
+ }
+
+ dsi_pll_res->vco_cached_rate = c->rate;
+ dsi_pll_disable(c);
+}
+
+static void pll_20nm_config_resetsm(void __iomem *pll_base)
+{
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_RESETSM_CNTRL, 0x24);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_RESETSM_CNTRL2, 0x07);
+}
+
+static void pll_20nm_config_vco_start(void __iomem *pll_base)
+{
+
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN, 0x03);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_RESETSM_CNTRL3, 0x02);
+ MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_RESETSM_CNTRL3, 0x03);
+}
+
+static int pll_20nm_vco_init_lock(struct mdss_pll_resources *dsi_pll_res)
+{
+ int rc = 0;
+ struct mdss_pll_vco_calc vco_calc;
+
+ pll_20nm_config_common_block(dsi_pll_res->pll_base);
+ pll_20nm_config_loop_bw(dsi_pll_res->pll_base);
+
+ pll_20nm_vco_rate_calc(&vco_calc, dsi_pll_res->vco_current_rate,
+ dsi_pll_res->vco_ref_clk_rate);
+ pll_20nm_config_vco_rate(dsi_pll_res->pll_base, &vco_calc);
+
+ pll_20nm_config_resetsm(dsi_pll_res->pll_base);
+ pll_20nm_config_vco_start(dsi_pll_res->pll_base);
+
+ if (!pll_20nm_is_pll_locked(dsi_pll_res)) {
+ pr_err("DSI PLL lock failed\n");
+ rc = -EINVAL;
+ goto init_lock_err;
+ }
+
+ pr_debug("DSI PLL Lock success\n");
+ pll_20nm_cache_trim_codes(dsi_pll_res);
+
+init_lock_err:
+ return rc;
+}
+
+int pll_20nm_vco_enable_seq(struct mdss_pll_resources *dsi_pll_res)
+{
+ int rc = 0;
+
+ if (!dsi_pll_res) {
+ pr_err("Invalid PLL resources\n");
+ return -EINVAL;
+ }
+
+ rc = pll_20nm_vco_init_lock(dsi_pll_res);
+
+ return rc;
+}
diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll-20nm.c b/drivers/clk/qcom/mdss/mdss-dsi-pll-20nm.c
new file mode 100644
index 0000000..de739c0d
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-dsi-pll-20nm.c
@@ -0,0 +1,608 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/clk/msm-clk-provider.h>
+#include <linux/clk/msm-clk.h>
+#include <linux/workqueue.h>
+#include <linux/clk/msm-clock-generic.h>
+#include <dt-bindings/clock/msm-clocks-8994.h>
+
+#include "mdss-pll.h"
+#include "mdss-dsi-pll.h"
+
+#define VCO_DELAY_USEC 1
+
+static const struct clk_ops bypass_lp_div_mux_clk_ops;
+static const struct clk_ops pixel_clk_src_ops;
+static const struct clk_ops byte_clk_src_ops;
+static const struct clk_ops ndiv_clk_ops;
+
+static const struct clk_ops shadow_pixel_clk_src_ops;
+static const struct clk_ops shadow_byte_clk_src_ops;
+static const struct clk_ops clk_ops_gen_mux_dsi;
+
+static int vco_set_rate_20nm(struct clk *c, unsigned long rate)
+{
+ int rc;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ pr_debug("Cancel pending pll off work\n");
+ cancel_work_sync(&dsi_pll_res->pll_off);
+ rc = pll_20nm_vco_set_rate(vco, rate);
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return rc;
+}
+
+static int pll1_vco_set_rate_20nm(struct clk *c, unsigned long rate)
+{
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *pll_res = vco->priv;
+
+ mdss_pll_resource_enable(pll_res, true);
+ __dsi_pll_disable(pll_res->pll_base);
+ mdss_pll_resource_enable(pll_res, false);
+
+ pr_debug("Configuring PLL1 registers.\n");
+
+ return 0;
+}
+
+static int shadow_vco_set_rate_20nm(struct clk *c, unsigned long rate)
+{
+ int rc;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ if (!dsi_pll_res->resource_enable) {
+ pr_err("PLL resources disabled. Dynamic fps invalid\n");
+ return -EINVAL;
+ }
+
+ rc = shadow_pll_20nm_vco_set_rate(vco, rate);
+
+ return rc;
+}
+
+/* Op structures */
+
+static const struct clk_ops pll1_clk_ops_dsi_vco = {
+ .set_rate = pll1_vco_set_rate_20nm,
+};
+
+static const struct clk_ops clk_ops_dsi_vco = {
+ .set_rate = vco_set_rate_20nm,
+ .round_rate = pll_20nm_vco_round_rate,
+ .handoff = pll_20nm_vco_handoff,
+ .prepare = pll_20nm_vco_prepare,
+ .unprepare = pll_20nm_vco_unprepare,
+};
+
+static struct clk_div_ops fixed_hr_oclk2_div_ops = {
+ .set_div = fixed_hr_oclk2_set_div,
+ .get_div = fixed_hr_oclk2_get_div,
+};
+
+static struct clk_div_ops ndiv_ops = {
+ .set_div = ndiv_set_div,
+ .get_div = ndiv_get_div,
+};
+
+static struct clk_div_ops hr_oclk3_div_ops = {
+ .set_div = hr_oclk3_set_div,
+ .get_div = hr_oclk3_get_div,
+};
+
+static struct clk_mux_ops bypass_lp_div_mux_ops = {
+ .set_mux_sel = set_bypass_lp_div_mux_sel,
+ .get_mux_sel = get_bypass_lp_div_mux_sel,
+};
+
+static const struct clk_ops shadow_clk_ops_dsi_vco = {
+ .set_rate = shadow_vco_set_rate_20nm,
+ .round_rate = pll_20nm_vco_round_rate,
+ .handoff = pll_20nm_vco_handoff,
+};
+
+static struct clk_div_ops shadow_fixed_hr_oclk2_div_ops = {
+ .set_div = shadow_fixed_hr_oclk2_set_div,
+ .get_div = fixed_hr_oclk2_get_div,
+};
+
+static struct clk_div_ops shadow_ndiv_ops = {
+ .set_div = shadow_ndiv_set_div,
+ .get_div = ndiv_get_div,
+};
+
+static struct clk_div_ops shadow_hr_oclk3_div_ops = {
+ .set_div = shadow_hr_oclk3_set_div,
+ .get_div = hr_oclk3_get_div,
+};
+
+static struct clk_mux_ops shadow_bypass_lp_div_mux_ops = {
+ .set_mux_sel = set_shadow_bypass_lp_div_mux_sel,
+ .get_mux_sel = get_bypass_lp_div_mux_sel,
+};
+
+static struct clk_mux_ops mdss_byte_mux_ops = {
+ .set_mux_sel = set_mdss_byte_mux_sel,
+ .get_mux_sel = get_mdss_byte_mux_sel,
+};
+
+static struct clk_mux_ops mdss_pixel_mux_ops = {
+ .set_mux_sel = set_mdss_pixel_mux_sel,
+ .get_mux_sel = get_mdss_pixel_mux_sel,
+};
+
+static struct dsi_pll_vco_clk mdss_dsi1_vco_clk_src = {
+ .c = {
+ .dbg_name = "mdss_dsi1_vco_clk_src",
+ .ops = &pll1_clk_ops_dsi_vco,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(mdss_dsi1_vco_clk_src.c),
+ },
+};
+
+static struct dsi_pll_vco_clk dsi_vco_clk_8994 = {
+ .ref_clk_rate = 19200000,
+ .min_rate = 300000000,
+ .max_rate = 1500000000,
+ .pll_en_seq_cnt = 1,
+ .pll_enable_seqs[0] = pll_20nm_vco_enable_seq,
+ .c = {
+ .dbg_name = "dsi_vco_clk_8994",
+ .ops = &clk_ops_dsi_vco,
+ CLK_INIT(dsi_vco_clk_8994.c),
+ },
+};
+
+static struct dsi_pll_vco_clk shadow_dsi_vco_clk_8994 = {
+ .ref_clk_rate = 19200000,
+ .min_rate = 300000000,
+ .max_rate = 1500000000,
+ .c = {
+ .dbg_name = "shadow_dsi_vco_clk_8994",
+ .ops = &shadow_clk_ops_dsi_vco,
+ CLK_INIT(shadow_dsi_vco_clk_8994.c),
+ },
+};
+
+static struct div_clk ndiv_clk_8994 = {
+ .data = {
+ .max_div = 15,
+ .min_div = 1,
+ },
+ .ops = &ndiv_ops,
+ .c = {
+ .parent = &dsi_vco_clk_8994.c,
+ .dbg_name = "ndiv_clk_8994",
+ .ops = &ndiv_clk_ops,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(ndiv_clk_8994.c),
+ },
+};
+
+static struct div_clk shadow_ndiv_clk_8994 = {
+ .data = {
+ .max_div = 15,
+ .min_div = 1,
+ },
+ .ops = &shadow_ndiv_ops,
+ .c = {
+ .parent = &shadow_dsi_vco_clk_8994.c,
+ .dbg_name = "shadow_ndiv_clk_8994",
+ .ops = &clk_ops_div,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(shadow_ndiv_clk_8994.c),
+ },
+};
+
+static struct div_clk indirect_path_div2_clk_8994 = {
+ .data = {
+ .div = 2,
+ .min_div = 2,
+ .max_div = 2,
+ },
+ .c = {
+ .parent = &ndiv_clk_8994.c,
+ .dbg_name = "indirect_path_div2_clk_8994",
+ .ops = &clk_ops_div,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(indirect_path_div2_clk_8994.c),
+ },
+};
+
+static struct div_clk shadow_indirect_path_div2_clk_8994 = {
+ .data = {
+ .div = 2,
+ .min_div = 2,
+ .max_div = 2,
+ },
+ .c = {
+ .parent = &shadow_ndiv_clk_8994.c,
+ .dbg_name = "shadow_indirect_path_div2_clk_8994",
+ .ops = &clk_ops_div,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(shadow_indirect_path_div2_clk_8994.c),
+ },
+};
+
+static struct div_clk hr_oclk3_div_clk_8994 = {
+ .data = {
+ .max_div = 255,
+ .min_div = 1,
+ },
+ .ops = &hr_oclk3_div_ops,
+ .c = {
+ .parent = &dsi_vco_clk_8994.c,
+ .dbg_name = "hr_oclk3_div_clk_8994",
+ .ops = &pixel_clk_src_ops,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(hr_oclk3_div_clk_8994.c),
+ },
+};
+
+static struct div_clk shadow_hr_oclk3_div_clk_8994 = {
+ .data = {
+ .max_div = 255,
+ .min_div = 1,
+ },
+ .ops = &shadow_hr_oclk3_div_ops,
+ .c = {
+ .parent = &shadow_dsi_vco_clk_8994.c,
+ .dbg_name = "shadow_hr_oclk3_div_clk_8994",
+ .ops = &shadow_pixel_clk_src_ops,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(shadow_hr_oclk3_div_clk_8994.c),
+ },
+};
+
+static struct div_clk pixel_clk_src = {
+ .data = {
+ .div = 2,
+ .min_div = 2,
+ .max_div = 2,
+ },
+ .c = {
+ .parent = &hr_oclk3_div_clk_8994.c,
+ .dbg_name = "pixel_clk_src",
+ .ops = &clk_ops_div,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(pixel_clk_src.c),
+ },
+};
+
+static struct div_clk shadow_pixel_clk_src = {
+ .data = {
+ .div = 2,
+ .min_div = 2,
+ .max_div = 2,
+ },
+ .c = {
+ .parent = &shadow_hr_oclk3_div_clk_8994.c,
+ .dbg_name = "shadow_pixel_clk_src",
+ .ops = &clk_ops_div,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(shadow_pixel_clk_src.c),
+ },
+};
+
+static struct mux_clk bypass_lp_div_mux_8994 = {
+ .num_parents = 2,
+ .parents = (struct clk_src[]){
+ {&dsi_vco_clk_8994.c, 0},
+ {&indirect_path_div2_clk_8994.c, 1},
+ },
+ .ops = &bypass_lp_div_mux_ops,
+ .c = {
+ .parent = &dsi_vco_clk_8994.c,
+ .dbg_name = "bypass_lp_div_mux_8994",
+ .ops = &bypass_lp_div_mux_clk_ops,
+ CLK_INIT(bypass_lp_div_mux_8994.c),
+ },
+};
+
+static struct mux_clk shadow_bypass_lp_div_mux_8994 = {
+ .num_parents = 2,
+ .parents = (struct clk_src[]){
+ {&shadow_dsi_vco_clk_8994.c, 0},
+ {&shadow_indirect_path_div2_clk_8994.c, 1},
+ },
+ .ops = &shadow_bypass_lp_div_mux_ops,
+ .c = {
+ .parent = &shadow_dsi_vco_clk_8994.c,
+ .dbg_name = "shadow_bypass_lp_div_mux_8994",
+ .ops = &clk_ops_gen_mux,
+ CLK_INIT(shadow_bypass_lp_div_mux_8994.c),
+ },
+};
+
+static struct div_clk fixed_hr_oclk2_div_clk_8994 = {
+ .ops = &fixed_hr_oclk2_div_ops,
+ .data = {
+ .min_div = 4,
+ .max_div = 4,
+ },
+ .c = {
+ .parent = &bypass_lp_div_mux_8994.c,
+ .dbg_name = "fixed_hr_oclk2_div_clk_8994",
+ .ops = &byte_clk_src_ops,
+ CLK_INIT(fixed_hr_oclk2_div_clk_8994.c),
+ },
+};
+
+static struct div_clk shadow_fixed_hr_oclk2_div_clk_8994 = {
+ .ops = &shadow_fixed_hr_oclk2_div_ops,
+ .data = {
+ .min_div = 4,
+ .max_div = 4,
+ },
+ .c = {
+ .parent = &shadow_bypass_lp_div_mux_8994.c,
+ .dbg_name = "shadow_fixed_hr_oclk2_div_clk_8994",
+ .ops = &shadow_byte_clk_src_ops,
+ CLK_INIT(shadow_fixed_hr_oclk2_div_clk_8994.c),
+ },
+};
+
+static struct div_clk byte_clk_src = {
+ .data = {
+ .div = 2,
+ .min_div = 2,
+ .max_div = 2,
+ },
+ .c = {
+ .parent = &fixed_hr_oclk2_div_clk_8994.c,
+ .dbg_name = "byte_clk_src",
+ .ops = &clk_ops_div,
+ CLK_INIT(byte_clk_src.c),
+ },
+};
+
+static struct div_clk shadow_byte_clk_src = {
+ .data = {
+ .div = 2,
+ .min_div = 2,
+ .max_div = 2,
+ },
+ .c = {
+ .parent = &shadow_fixed_hr_oclk2_div_clk_8994.c,
+ .dbg_name = "shadow_byte_clk_src",
+ .ops = &clk_ops_div,
+ CLK_INIT(shadow_byte_clk_src.c),
+ },
+};
+
+static struct mux_clk mdss_pixel_clk_mux = {
+ .num_parents = 2,
+ .parents = (struct clk_src[]) {
+ {&pixel_clk_src.c, 0},
+ {&shadow_pixel_clk_src.c, 1},
+ },
+ .ops = &mdss_pixel_mux_ops,
+ .c = {
+ .parent = &pixel_clk_src.c,
+ .dbg_name = "mdss_pixel_clk_mux",
+ .ops = &clk_ops_gen_mux,
+ CLK_INIT(mdss_pixel_clk_mux.c),
+ }
+};
+
+static struct mux_clk mdss_byte_clk_mux = {
+ .num_parents = 2,
+ .parents = (struct clk_src[]) {
+ {&byte_clk_src.c, 0},
+ {&shadow_byte_clk_src.c, 1},
+ },
+ .ops = &mdss_byte_mux_ops,
+ .c = {
+ .parent = &byte_clk_src.c,
+ .dbg_name = "mdss_byte_clk_mux",
+ .ops = &clk_ops_gen_mux_dsi,
+ CLK_INIT(mdss_byte_clk_mux.c),
+ }
+};
+
+static struct clk_lookup mdss_dsi_pll_1_cc_8994[] = {
+ CLK_LIST(mdss_dsi1_vco_clk_src),
+};
+
+static struct clk_lookup mdss_dsi_pllcc_8994[] = {
+ CLK_LIST(mdss_pixel_clk_mux),
+ CLK_LIST(mdss_byte_clk_mux),
+ CLK_LIST(pixel_clk_src),
+ CLK_LIST(byte_clk_src),
+ CLK_LIST(fixed_hr_oclk2_div_clk_8994),
+ CLK_LIST(bypass_lp_div_mux_8994),
+ CLK_LIST(hr_oclk3_div_clk_8994),
+ CLK_LIST(indirect_path_div2_clk_8994),
+ CLK_LIST(ndiv_clk_8994),
+ CLK_LIST(dsi_vco_clk_8994),
+ CLK_LIST(shadow_pixel_clk_src),
+ CLK_LIST(shadow_byte_clk_src),
+ CLK_LIST(shadow_fixed_hr_oclk2_div_clk_8994),
+ CLK_LIST(shadow_bypass_lp_div_mux_8994),
+ CLK_LIST(shadow_hr_oclk3_div_clk_8994),
+ CLK_LIST(shadow_indirect_path_div2_clk_8994),
+ CLK_LIST(shadow_ndiv_clk_8994),
+ CLK_LIST(shadow_dsi_vco_clk_8994),
+};
+
+static void dsi_pll_off_work(struct work_struct *work)
+{
+ struct mdss_pll_resources *pll_res;
+
+ if (!work) {
+ pr_err("pll_resource is invalid\n");
+ return;
+ }
+
+ pr_debug("Starting PLL off Worker%s\n", __func__);
+
+ pll_res = container_of(work, struct
+ mdss_pll_resources, pll_off);
+
+ mdss_pll_resource_enable(pll_res, true);
+ __dsi_pll_disable(pll_res->pll_base);
+ if (pll_res->pll_1_base)
+ __dsi_pll_disable(pll_res->pll_1_base);
+ mdss_pll_resource_enable(pll_res, false);
+}
+
+static int dsi_pll_regulator_notifier_call(struct notifier_block *self,
+ unsigned long event, void *data)
+{
+
+ struct mdss_pll_resources *pll_res;
+
+ if (!self) {
+ pr_err("pll_resource is invalid\n");
+ goto error;
+ }
+
+ pll_res = container_of(self, struct
+ mdss_pll_resources, gdsc_cb);
+
+ if (event & REGULATOR_EVENT_ENABLE) {
+ pr_debug("Regulator ON event. Scheduling pll off worker\n");
+ schedule_work(&pll_res->pll_off);
+ }
+
+ if (event & REGULATOR_EVENT_DISABLE)
+ pr_debug("Regulator OFF event.\n");
+
+error:
+ return NOTIFY_OK;
+}
+
+int dsi_pll_clock_register_20nm(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ int rc;
+ struct dss_vreg *pll_reg;
+
+ if (!pdev || !pdev->dev.of_node) {
+ pr_err("Invalid input parameters\n");
+ return -EINVAL;
+ }
+
+ if (!pll_res || !pll_res->pll_base) {
+ pr_err("Invalid PLL resources\n");
+ return -EPROBE_DEFER;
+ }
+
+ /*
+ * Set client data to mux, div and vco clocks.
+ * This needs to be done only for PLL0 since, that is the one in
+ * use.
+ **/
+ if (!pll_res->index) {
+ byte_clk_src.priv = pll_res;
+ pixel_clk_src.priv = pll_res;
+ bypass_lp_div_mux_8994.priv = pll_res;
+ indirect_path_div2_clk_8994.priv = pll_res;
+ ndiv_clk_8994.priv = pll_res;
+ fixed_hr_oclk2_div_clk_8994.priv = pll_res;
+ hr_oclk3_div_clk_8994.priv = pll_res;
+ dsi_vco_clk_8994.priv = pll_res;
+
+ shadow_byte_clk_src.priv = pll_res;
+ shadow_pixel_clk_src.priv = pll_res;
+ shadow_bypass_lp_div_mux_8994.priv = pll_res;
+ shadow_indirect_path_div2_clk_8994.priv = pll_res;
+ shadow_ndiv_clk_8994.priv = pll_res;
+ shadow_fixed_hr_oclk2_div_clk_8994.priv = pll_res;
+ shadow_hr_oclk3_div_clk_8994.priv = pll_res;
+ shadow_dsi_vco_clk_8994.priv = pll_res;
+
+ pll_res->vco_delay = VCO_DELAY_USEC;
+
+ /* Set clock source operations */
+ pixel_clk_src_ops = clk_ops_slave_div;
+ pixel_clk_src_ops.prepare = dsi_pll_div_prepare;
+
+ ndiv_clk_ops = clk_ops_div;
+ ndiv_clk_ops.prepare = dsi_pll_div_prepare;
+
+ byte_clk_src_ops = clk_ops_div;
+ byte_clk_src_ops.prepare = dsi_pll_div_prepare;
+
+ bypass_lp_div_mux_clk_ops = clk_ops_gen_mux;
+ bypass_lp_div_mux_clk_ops.prepare = dsi_pll_mux_prepare;
+
+ clk_ops_gen_mux_dsi = clk_ops_gen_mux;
+ clk_ops_gen_mux_dsi.round_rate = parent_round_rate;
+ clk_ops_gen_mux_dsi.set_rate = parent_set_rate;
+
+ shadow_pixel_clk_src_ops = clk_ops_slave_div;
+ shadow_pixel_clk_src_ops.prepare = dsi_pll_div_prepare;
+
+ shadow_byte_clk_src_ops = clk_ops_div;
+ shadow_byte_clk_src_ops.prepare = dsi_pll_div_prepare;
+ } else {
+ mdss_dsi1_vco_clk_src.priv = pll_res;
+ }
+
+ if ((pll_res->target_id == MDSS_PLL_TARGET_8994) ||
+ (pll_res->target_id == MDSS_PLL_TARGET_8992)) {
+ if (pll_res->index) {
+ rc = of_msm_clock_register(pdev->dev.of_node,
+ mdss_dsi_pll_1_cc_8994,
+ ARRAY_SIZE(mdss_dsi_pll_1_cc_8994));
+ if (rc) {
+ pr_err("Clock register failed\n");
+ rc = -EPROBE_DEFER;
+ }
+ } else {
+ rc = of_msm_clock_register(pdev->dev.of_node,
+ mdss_dsi_pllcc_8994,
+ ARRAY_SIZE(mdss_dsi_pllcc_8994));
+ if (rc) {
+ pr_err("Clock register failed\n");
+ rc = -EPROBE_DEFER;
+ }
+ pll_res->gdsc_cb.notifier_call =
+ dsi_pll_regulator_notifier_call;
+ INIT_WORK(&pll_res->pll_off, dsi_pll_off_work);
+
+ pll_reg = mdss_pll_get_mp_by_reg_name(pll_res, "gdsc");
+ if (pll_reg) {
+ pr_debug("Registering for gdsc regulator events\n");
+ if (regulator_register_notifier(pll_reg->vreg,
+ &(pll_res->gdsc_cb)))
+ pr_err("Regulator notification registration failed!\n");
+ }
+ }
+
+ } else {
+ pr_err("Invalid target ID\n");
+ rc = -EINVAL;
+ }
+
+ if (!rc)
+ pr_info("Registered DSI PLL clocks successfully\n");
+
+ return rc;
+}
diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll-28hpm.c b/drivers/clk/qcom/mdss/mdss-dsi-pll-28hpm.c
new file mode 100644
index 0000000..61c49c2
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-dsi-pll-28hpm.c
@@ -0,0 +1,335 @@
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/clk/msm-clk-provider.h>
+#include <linux/clk/msm-clk.h>
+#include <linux/clk/msm-clock-generic.h>
+#include <dt-bindings/clock/msm-clocks-8974.h>
+
+#include "mdss-pll.h"
+#include "mdss-dsi-pll.h"
+
+#define VCO_DELAY_USEC 1
+
+static struct clk_div_ops fixed_2div_ops;
+static const struct clk_ops byte_mux_clk_ops;
+static const struct clk_ops pixel_clk_src_ops;
+static const struct clk_ops byte_clk_src_ops;
+static const struct clk_ops analog_postdiv_clk_ops;
+static struct lpfr_cfg lpfr_lut_struct[] = {
+ {479500000, 8},
+ {480000000, 11},
+ {575500000, 8},
+ {576000000, 12},
+ {610500000, 8},
+ {659500000, 9},
+ {671500000, 10},
+ {672000000, 14},
+ {708500000, 10},
+ {750000000, 11},
+};
+
+static void dsi_pll_software_reset(struct mdss_pll_resources *dsi_pll_res)
+{
+ /*
+ * Add HW recommended delays after toggling the software
+ * reset bit off and back on.
+ */
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x01);
+ udelay(1);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x00);
+ udelay(1);
+}
+
+static int vco_set_rate_hpm(struct clk *c, unsigned long rate)
+{
+ int rc;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ rc = vco_set_rate(vco, rate);
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return rc;
+}
+
+static int dsi_pll_enable_seq_8974(struct mdss_pll_resources *dsi_pll_res)
+{
+ int i, rc = 0;
+ int pll_locked;
+
+ dsi_pll_software_reset(dsi_pll_res);
+
+ /*
+ * PLL power up sequence.
+ * Add necessary delays recommeded by hardware.
+ */
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
+ udelay(1);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
+ udelay(200);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07);
+ udelay(500);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
+ udelay(500);
+
+ for (i = 0; i < 2; i++) {
+ udelay(100);
+ /* DSI Uniphy lock detect setting */
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0c);
+ udelay(100);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d);
+
+ pll_locked = dsi_pll_lock_status(dsi_pll_res);
+ if (pll_locked)
+ break;
+
+ dsi_pll_software_reset(dsi_pll_res);
+ /*
+ * PLL power up sequence.
+ * Add necessary delays recommeded by hardware.
+ */
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x1);
+ udelay(1);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x5);
+ udelay(200);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x7);
+ udelay(250);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x5);
+ udelay(200);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x7);
+ udelay(500);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0xf);
+ udelay(500);
+
+ }
+
+ if (!pll_locked) {
+ pr_err("DSI PLL lock failed\n");
+ rc = -EINVAL;
+ } else {
+ pr_debug("DSI PLL Lock success\n");
+ }
+
+ return rc;
+}
+
+/* Op structures */
+
+static const struct clk_ops clk_ops_dsi_vco = {
+ .set_rate = vco_set_rate_hpm,
+ .round_rate = vco_round_rate,
+ .handoff = vco_handoff,
+ .prepare = vco_prepare,
+ .unprepare = vco_unprepare,
+};
+
+
+static struct clk_div_ops fixed_4div_ops = {
+ .set_div = fixed_4div_set_div,
+ .get_div = fixed_4div_get_div,
+};
+
+static struct clk_div_ops analog_postdiv_ops = {
+ .set_div = analog_set_div,
+ .get_div = analog_get_div,
+};
+
+static struct clk_div_ops digital_postdiv_ops = {
+ .set_div = digital_set_div,
+ .get_div = digital_get_div,
+};
+
+static struct clk_mux_ops byte_mux_ops = {
+ .set_mux_sel = set_byte_mux_sel,
+ .get_mux_sel = get_byte_mux_sel,
+};
+
+static struct dsi_pll_vco_clk dsi_vco_clk_8974 = {
+ .ref_clk_rate = 19200000,
+ .min_rate = 350000000,
+ .max_rate = 750000000,
+ .pll_en_seq_cnt = 3,
+ .pll_enable_seqs[0] = dsi_pll_enable_seq_8974,
+ .pll_enable_seqs[1] = dsi_pll_enable_seq_8974,
+ .pll_enable_seqs[2] = dsi_pll_enable_seq_8974,
+ .lpfr_lut_size = 10,
+ .lpfr_lut = lpfr_lut_struct,
+ .c = {
+ .dbg_name = "dsi_vco_clk_8974",
+ .ops = &clk_ops_dsi_vco,
+ CLK_INIT(dsi_vco_clk_8974.c),
+ },
+};
+
+static struct div_clk analog_postdiv_clk_8974 = {
+ .data = {
+ .max_div = 255,
+ .min_div = 1,
+ },
+ .ops = &analog_postdiv_ops,
+ .c = {
+ .parent = &dsi_vco_clk_8974.c,
+ .dbg_name = "analog_postdiv_clk",
+ .ops = &analog_postdiv_clk_ops,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(analog_postdiv_clk_8974.c),
+ },
+};
+
+static struct div_clk indirect_path_div2_clk_8974 = {
+ .ops = &fixed_2div_ops,
+ .data = {
+ .div = 2,
+ .min_div = 2,
+ .max_div = 2,
+ },
+ .c = {
+ .parent = &analog_postdiv_clk_8974.c,
+ .dbg_name = "indirect_path_div2_clk",
+ .ops = &clk_ops_div,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(indirect_path_div2_clk_8974.c),
+ },
+};
+
+static struct div_clk pixel_clk_src_8974 = {
+ .data = {
+ .max_div = 255,
+ .min_div = 1,
+ },
+ .ops = &digital_postdiv_ops,
+ .c = {
+ .parent = &dsi_vco_clk_8974.c,
+ .dbg_name = "pixel_clk_src_8974",
+ .ops = &pixel_clk_src_ops,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(pixel_clk_src_8974.c),
+ },
+};
+
+static struct mux_clk byte_mux_8974 = {
+ .num_parents = 2,
+ .parents = (struct clk_src[]){
+ {&dsi_vco_clk_8974.c, 0},
+ {&indirect_path_div2_clk_8974.c, 1},
+ },
+ .ops = &byte_mux_ops,
+ .c = {
+ .parent = &dsi_vco_clk_8974.c,
+ .dbg_name = "byte_mux_8974",
+ .ops = &byte_mux_clk_ops,
+ CLK_INIT(byte_mux_8974.c),
+ },
+};
+
+static struct div_clk byte_clk_src_8974 = {
+ .ops = &fixed_4div_ops,
+ .data = {
+ .min_div = 4,
+ .max_div = 4,
+ },
+ .c = {
+ .parent = &byte_mux_8974.c,
+ .dbg_name = "byte_clk_src_8974",
+ .ops = &byte_clk_src_ops,
+ CLK_INIT(byte_clk_src_8974.c),
+ },
+};
+
+static struct clk_lookup mdss_dsi_pllcc_8974[] = {
+ CLK_LOOKUP_OF("pixel_src", pixel_clk_src_8974,
+ "fd8c0000.qcom,mmsscc-mdss"),
+ CLK_LOOKUP_OF("byte_src", byte_clk_src_8974,
+ "fd8c0000.qcom,mmsscc-mdss"),
+};
+
+int dsi_pll_clock_register_hpm(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ int rc;
+
+ if (!pdev || !pdev->dev.of_node) {
+ pr_err("Invalid input parameters\n");
+ return -EINVAL;
+ }
+
+ if (!pll_res || !pll_res->pll_base) {
+ pr_err("Invalid PLL resources\n");
+ return -EPROBE_DEFER;
+ }
+
+ /* Set client data to mux, div and vco clocks */
+ byte_clk_src_8974.priv = pll_res;
+ pixel_clk_src_8974.priv = pll_res;
+ byte_mux_8974.priv = pll_res;
+ indirect_path_div2_clk_8974.priv = pll_res;
+ analog_postdiv_clk_8974.priv = pll_res;
+ dsi_vco_clk_8974.priv = pll_res;
+ pll_res->vco_delay = VCO_DELAY_USEC;
+
+ /* Set clock source operations */
+ pixel_clk_src_ops = clk_ops_slave_div;
+ pixel_clk_src_ops.prepare = dsi_pll_div_prepare;
+
+ analog_postdiv_clk_ops = clk_ops_div;
+ analog_postdiv_clk_ops.prepare = dsi_pll_div_prepare;
+
+ byte_clk_src_ops = clk_ops_div;
+ byte_clk_src_ops.prepare = dsi_pll_div_prepare;
+
+ byte_mux_clk_ops = clk_ops_gen_mux;
+ byte_mux_clk_ops.prepare = dsi_pll_mux_prepare;
+
+ if (pll_res->target_id == MDSS_PLL_TARGET_8974) {
+ rc = of_msm_clock_register(pdev->dev.of_node,
+ mdss_dsi_pllcc_8974, ARRAY_SIZE(mdss_dsi_pllcc_8974));
+ if (rc) {
+ pr_err("Clock register failed\n");
+ rc = -EPROBE_DEFER;
+ }
+ } else {
+ pr_err("Invalid target ID\n");
+ rc = -EINVAL;
+ }
+
+ if (!rc)
+ pr_info("Registered DSI PLL clocks successfully\n");
+
+ return rc;
+}
diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll-28lpm.c b/drivers/clk/qcom/mdss/mdss-dsi-pll-28lpm.c
new file mode 100644
index 0000000..8ffc03f
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-dsi-pll-28lpm.c
@@ -0,0 +1,306 @@
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/clk/msm-clk.h>
+#include <linux/clk/msm-clock-generic.h>
+#include <linux/clk/msm-clk-provider.h>
+#include <dt-bindings/clock/msm-clocks-8916.h>
+
+#include "mdss-pll.h"
+#include "mdss-dsi-pll.h"
+
+#define VCO_DELAY_USEC 1000
+
+static struct clk_div_ops fixed_2div_ops;
+static const struct clk_ops byte_mux_clk_ops;
+static const struct clk_ops pixel_clk_src_ops;
+static const struct clk_ops byte_clk_src_ops;
+static const struct clk_ops analog_postdiv_clk_ops;
+static struct lpfr_cfg lpfr_lut_struct[] = {
+ {479500000, 8},
+ {480000000, 11},
+ {575500000, 8},
+ {576000000, 12},
+ {610500000, 8},
+ {659500000, 9},
+ {671500000, 10},
+ {672000000, 14},
+ {708500000, 10},
+ {750000000, 11},
+};
+
+static int vco_set_rate_lpm(struct clk *c, unsigned long rate)
+{
+ int rc;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ /*
+ * DSI PLL software reset. Add HW recommended delays after toggling
+ * the software reset bit off and back on.
+ */
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x01);
+ udelay(1000);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x00);
+ udelay(1000);
+
+ rc = vco_set_rate(vco, rate);
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return rc;
+}
+
+static int dsi_pll_enable_seq_8916(struct mdss_pll_resources *dsi_pll_res)
+{
+ int pll_locked = 0;
+
+ /*
+ * DSI PLL software reset. Add HW recommended delays after toggling
+ * the software reset bit off and back on.
+ */
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x01);
+ ndelay(500);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x00);
+
+ /*
+ * PLL power up sequence.
+ * Add necessary delays recommended by hardware.
+ */
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1, 0x34);
+ ndelay(500);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
+ ndelay(500);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
+ ndelay(500);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
+ ndelay(500);
+
+ /* DSI PLL toggle lock detect setting */
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x04);
+ ndelay(500);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x05);
+ udelay(512);
+
+ pll_locked = dsi_pll_lock_status(dsi_pll_res);
+
+ if (pll_locked)
+ pr_debug("PLL Locked\n");
+ else
+ pr_err("PLL failed to lock\n");
+
+ return pll_locked ? 0 : -EINVAL;
+}
+
+/* Op structures */
+
+static const struct clk_ops clk_ops_dsi_vco = {
+ .set_rate = vco_set_rate_lpm,
+ .round_rate = vco_round_rate,
+ .handoff = vco_handoff,
+ .prepare = vco_prepare,
+ .unprepare = vco_unprepare,
+};
+
+
+static struct clk_div_ops fixed_4div_ops = {
+ .set_div = fixed_4div_set_div,
+ .get_div = fixed_4div_get_div,
+};
+
+static struct clk_div_ops analog_postdiv_ops = {
+ .set_div = analog_set_div,
+ .get_div = analog_get_div,
+};
+
+static struct clk_div_ops digital_postdiv_ops = {
+ .set_div = digital_set_div,
+ .get_div = digital_get_div,
+};
+
+static struct clk_mux_ops byte_mux_ops = {
+ .set_mux_sel = set_byte_mux_sel,
+ .get_mux_sel = get_byte_mux_sel,
+};
+
+static struct dsi_pll_vco_clk dsi_vco_clk_8916 = {
+ .ref_clk_rate = 19200000,
+ .min_rate = 350000000,
+ .max_rate = 750000000,
+ .pll_en_seq_cnt = 1,
+ .pll_enable_seqs[0] = dsi_pll_enable_seq_8916,
+ .lpfr_lut_size = 10,
+ .lpfr_lut = lpfr_lut_struct,
+ .c = {
+ .dbg_name = "dsi_vco_clk_8916",
+ .ops = &clk_ops_dsi_vco,
+ CLK_INIT(dsi_vco_clk_8916.c),
+ },
+};
+
+static struct div_clk analog_postdiv_clk_8916 = {
+ .data = {
+ .max_div = 255,
+ .min_div = 1,
+ },
+ .ops = &analog_postdiv_ops,
+ .c = {
+ .parent = &dsi_vco_clk_8916.c,
+ .dbg_name = "analog_postdiv_clk",
+ .ops = &analog_postdiv_clk_ops,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(analog_postdiv_clk_8916.c),
+ },
+};
+
+static struct div_clk indirect_path_div2_clk_8916 = {
+ .ops = &fixed_2div_ops,
+ .data = {
+ .div = 2,
+ .min_div = 2,
+ .max_div = 2,
+ },
+ .c = {
+ .parent = &analog_postdiv_clk_8916.c,
+ .dbg_name = "indirect_path_div2_clk",
+ .ops = &clk_ops_div,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(indirect_path_div2_clk_8916.c),
+ },
+};
+
+static struct div_clk pixel_clk_src = {
+ .data = {
+ .max_div = 255,
+ .min_div = 1,
+ },
+ .ops = &digital_postdiv_ops,
+ .c = {
+ .parent = &dsi_vco_clk_8916.c,
+ .dbg_name = "pixel_clk_src_8916",
+ .ops = &pixel_clk_src_ops,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(pixel_clk_src.c),
+ },
+};
+
+static struct mux_clk byte_mux_8916 = {
+ .num_parents = 2,
+ .parents = (struct clk_src[]){
+ {&dsi_vco_clk_8916.c, 0},
+ {&indirect_path_div2_clk_8916.c, 1},
+ },
+ .ops = &byte_mux_ops,
+ .c = {
+ .parent = &dsi_vco_clk_8916.c,
+ .dbg_name = "byte_mux_8916",
+ .ops = &byte_mux_clk_ops,
+ CLK_INIT(byte_mux_8916.c),
+ },
+};
+
+static struct div_clk byte_clk_src = {
+ .ops = &fixed_4div_ops,
+ .data = {
+ .min_div = 4,
+ .max_div = 4,
+ },
+ .c = {
+ .parent = &byte_mux_8916.c,
+ .dbg_name = "byte_clk_src_8916",
+ .ops = &byte_clk_src_ops,
+ CLK_INIT(byte_clk_src.c),
+ },
+};
+
+static struct clk_lookup mdss_dsi_pllcc_8916[] = {
+ CLK_LIST(pixel_clk_src),
+ CLK_LIST(byte_clk_src),
+};
+
+int dsi_pll_clock_register_lpm(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ int rc;
+
+ if (!pdev || !pdev->dev.of_node) {
+ pr_err("Invalid input parameters\n");
+ return -EINVAL;
+ }
+
+ if (!pll_res || !pll_res->pll_base) {
+ pr_err("Invalid PLL resources\n");
+ return -EPROBE_DEFER;
+ }
+
+ /* Set client data to mux, div and vco clocks */
+ byte_clk_src.priv = pll_res;
+ pixel_clk_src.priv = pll_res;
+ byte_mux_8916.priv = pll_res;
+ indirect_path_div2_clk_8916.priv = pll_res;
+ analog_postdiv_clk_8916.priv = pll_res;
+ dsi_vco_clk_8916.priv = pll_res;
+ pll_res->vco_delay = VCO_DELAY_USEC;
+
+ /* Set clock source operations */
+ pixel_clk_src_ops = clk_ops_slave_div;
+ pixel_clk_src_ops.prepare = dsi_pll_div_prepare;
+
+ analog_postdiv_clk_ops = clk_ops_div;
+ analog_postdiv_clk_ops.prepare = dsi_pll_div_prepare;
+
+ byte_clk_src_ops = clk_ops_div;
+ byte_clk_src_ops.prepare = dsi_pll_div_prepare;
+
+ byte_mux_clk_ops = clk_ops_gen_mux;
+ byte_mux_clk_ops.prepare = dsi_pll_mux_prepare;
+
+ if (pll_res->target_id == MDSS_PLL_TARGET_8916 ||
+ pll_res->target_id == MDSS_PLL_TARGET_8939 ||
+ pll_res->target_id == MDSS_PLL_TARGET_8909) {
+ rc = of_msm_clock_register(pdev->dev.of_node,
+ mdss_dsi_pllcc_8916, ARRAY_SIZE(mdss_dsi_pllcc_8916));
+ if (rc) {
+ pr_err("Clock register failed\n");
+ rc = -EPROBE_DEFER;
+ }
+ } else {
+ pr_err("Invalid target ID\n");
+ rc = -EINVAL;
+ }
+
+ if (!rc)
+ pr_info("Registered DSI PLL clocks successfully\n");
+
+ return rc;
+}
diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll-util.c b/drivers/clk/qcom/mdss/mdss-dsi-pll-util.c
new file mode 100644
index 0000000..fd8d6cd
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-dsi-pll-util.c
@@ -0,0 +1,587 @@
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <linux/delay.h>
+#include <linux/clk/msm-clock-generic.h>
+
+#include "mdss-pll.h"
+#include "mdss-dsi-pll.h"
+
+#define DSI_PHY_PLL_UNIPHY_PLL_REFCLK_CFG (0x0)
+#define DSI_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG (0x0004)
+#define DSI_PHY_PLL_UNIPHY_PLL_CHGPUMP_CFG (0x0008)
+#define DSI_PHY_PLL_UNIPHY_PLL_VCOLPF_CFG (0x000C)
+#define DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG (0x0010)
+#define DSI_PHY_PLL_UNIPHY_PLL_PWRGEN_CFG (0x0014)
+#define DSI_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG (0x0024)
+#define DSI_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG (0x0028)
+#define DSI_PHY_PLL_UNIPHY_PLL_LPFR_CFG (0x002C)
+#define DSI_PHY_PLL_UNIPHY_PLL_LPFC1_CFG (0x0030)
+#define DSI_PHY_PLL_UNIPHY_PLL_LPFC2_CFG (0x0034)
+#define DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG0 (0x0038)
+#define DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG1 (0x003C)
+#define DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG2 (0x0040)
+#define DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG3 (0x0044)
+#define DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG4 (0x0048)
+#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG0 (0x006C)
+#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG2 (0x0074)
+#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG3 (0x0078)
+#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG4 (0x007C)
+#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG5 (0x0080)
+#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG6 (0x0084)
+#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG7 (0x0088)
+#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG8 (0x008C)
+#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG9 (0x0090)
+#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG10 (0x0094)
+#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG11 (0x0098)
+#define DSI_PHY_PLL_UNIPHY_PLL_EFUSE_CFG (0x009C)
+#define DSI_PHY_PLL_UNIPHY_PLL_STATUS (0x00C0)
+
+#define DSI_PLL_POLL_MAX_READS 10
+#define DSI_PLL_POLL_TIMEOUT_US 50
+
+int set_byte_mux_sel(struct mux_clk *clk, int sel)
+{
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ pr_debug("byte mux set to %s mode\n", sel ? "indirect" : "direct");
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG, (sel << 1));
+
+ return 0;
+}
+
+int get_byte_mux_sel(struct mux_clk *clk)
+{
+ int mux_mode, rc;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ if (is_gdsc_disabled(dsi_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ mux_mode = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG) & BIT(1);
+
+ pr_debug("byte mux mode = %s", mux_mode ? "indirect" : "direct");
+ mdss_pll_resource_enable(dsi_pll_res, false);
+
+ return !!mux_mode;
+}
+
+int dsi_pll_div_prepare(struct clk *c)
+{
+ struct div_clk *div = to_div_clk(c);
+ /* Restore the divider's value */
+ return div->ops->set_div(div, div->data.div);
+}
+
+int dsi_pll_mux_prepare(struct clk *c)
+{
+ struct mux_clk *mux = to_mux_clk(c);
+ int i, rc, sel = 0;
+ struct mdss_pll_resources *dsi_pll_res = mux->priv;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ for (i = 0; i < mux->num_parents; i++)
+ if (mux->parents[i].src == c->parent) {
+ sel = mux->parents[i].sel;
+ break;
+ }
+
+ if (i == mux->num_parents) {
+ pr_err("Failed to select the parent clock\n");
+ rc = -EINVAL;
+ goto error;
+ }
+
+ /* Restore the mux source select value */
+ rc = mux->ops->set_mux_sel(mux, sel);
+
+error:
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return rc;
+}
+
+int fixed_4div_set_div(struct div_clk *clk, int div)
+{
+ int rc;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG, (div - 1));
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return rc;
+}
+
+int fixed_4div_get_div(struct div_clk *clk)
+{
+ int div = 0, rc;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ if (is_gdsc_disabled(dsi_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ div = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG);
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return div + 1;
+}
+
+int digital_set_div(struct div_clk *clk, int div)
+{
+ int rc;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG, (div - 1));
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return rc;
+}
+
+int digital_get_div(struct div_clk *clk)
+{
+ int div = 0, rc;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ if (is_gdsc_disabled(dsi_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ div = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG);
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return div + 1;
+}
+
+int analog_set_div(struct div_clk *clk, int div)
+{
+ int rc;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG, div - 1);
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ return rc;
+}
+
+int analog_get_div(struct div_clk *clk)
+{
+ int div = 0, rc;
+ struct mdss_pll_resources *dsi_pll_res = clk->priv;
+
+ if (is_gdsc_disabled(dsi_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(clk->priv, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ div = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG) + 1;
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+
+ return div;
+}
+
+int dsi_pll_lock_status(struct mdss_pll_resources *dsi_pll_res)
+{
+ u32 status;
+ int pll_locked;
+
+ /* poll for PLL ready status */
+ if (readl_poll_timeout_atomic((dsi_pll_res->pll_base +
+ DSI_PHY_PLL_UNIPHY_PLL_STATUS),
+ status,
+ ((status & BIT(0)) == 1),
+ DSI_PLL_POLL_MAX_READS,
+ DSI_PLL_POLL_TIMEOUT_US)) {
+ pr_debug("DSI PLL status=%x failed to Lock\n", status);
+ pll_locked = 0;
+ } else {
+ pll_locked = 1;
+ }
+
+ return pll_locked;
+}
+
+int vco_set_rate(struct dsi_pll_vco_clk *vco, unsigned long rate)
+{
+ s64 vco_clk_rate = rate;
+ s32 rem;
+ s64 refclk_cfg, frac_n_mode, ref_doubler_en_b;
+ s64 ref_clk_to_pll, div_fbx1000, frac_n_value;
+ s64 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
+ s64 gen_vco_clk, cal_cfg10, cal_cfg11;
+ u32 res;
+ int i;
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ /* Configure the Loop filter resistance */
+ for (i = 0; i < vco->lpfr_lut_size; i++)
+ if (vco_clk_rate <= vco->lpfr_lut[i].vco_rate)
+ break;
+ if (i == vco->lpfr_lut_size) {
+ pr_err("unable to get loop filter resistance. vco=%ld\n", rate);
+ return -EINVAL;
+ }
+ res = vco->lpfr_lut[i].r;
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_LPFR_CFG, res);
+
+ /* Loop filter capacitance values : c1 and c2 */
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_LPFC1_CFG, 0x70);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_LPFC2_CFG, 0x15);
+
+ div_s64_rem(vco_clk_rate, vco->ref_clk_rate, &rem);
+ if (rem) {
+ refclk_cfg = 0x1;
+ frac_n_mode = 1;
+ ref_doubler_en_b = 0;
+ } else {
+ refclk_cfg = 0x0;
+ frac_n_mode = 0;
+ ref_doubler_en_b = 1;
+ }
+
+ pr_debug("refclk_cfg = %lld\n", refclk_cfg);
+
+ ref_clk_to_pll = ((vco->ref_clk_rate * 2 * (refclk_cfg))
+ + (ref_doubler_en_b * vco->ref_clk_rate));
+ div_fbx1000 = div_s64((vco_clk_rate * 1000), ref_clk_to_pll);
+
+ div_s64_rem(div_fbx1000, 1000, &rem);
+ frac_n_value = div_s64((rem * (1 << 16)), 1000);
+ gen_vco_clk = div_s64(div_fbx1000 * ref_clk_to_pll, 1000);
+
+ pr_debug("ref_clk_to_pll = %lld\n", ref_clk_to_pll);
+ pr_debug("div_fb = %lld\n", div_fbx1000);
+ pr_debug("frac_n_value = %lld\n", frac_n_value);
+
+ pr_debug("Generated VCO Clock: %lld\n", gen_vco_clk);
+ rem = 0;
+ if (frac_n_mode) {
+ sdm_cfg0 = (0x0 << 5);
+ sdm_cfg0 |= (0x0 & 0x3f);
+ sdm_cfg1 = (div_s64(div_fbx1000, 1000) & 0x3f) - 1;
+ sdm_cfg3 = div_s64_rem(frac_n_value, 256, &rem);
+ sdm_cfg2 = rem;
+ } else {
+ sdm_cfg0 = (0x1 << 5);
+ sdm_cfg0 |= (div_s64(div_fbx1000, 1000) & 0x3f) - 1;
+ sdm_cfg1 = (0x0 & 0x3f);
+ sdm_cfg2 = 0;
+ sdm_cfg3 = 0;
+ }
+
+ pr_debug("sdm_cfg0=%lld\n", sdm_cfg0);
+ pr_debug("sdm_cfg1=%lld\n", sdm_cfg1);
+ pr_debug("sdm_cfg2=%lld\n", sdm_cfg2);
+ pr_debug("sdm_cfg3=%lld\n", sdm_cfg3);
+
+ cal_cfg11 = div_s64_rem(gen_vco_clk, 256 * 1000000, &rem);
+ cal_cfg10 = rem / 1000000;
+ pr_debug("cal_cfg10=%lld, cal_cfg11=%lld\n", cal_cfg10, cal_cfg11);
+
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_CHGPUMP_CFG, 0x02);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG3, 0x2b);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG4, 0x66);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d);
+
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG1, (u32)(sdm_cfg1 & 0xff));
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG2, (u32)(sdm_cfg2 & 0xff));
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG3, (u32)(sdm_cfg3 & 0xff));
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG4, 0x00);
+
+ /* Add hardware recommended delay for correct PLL configuration */
+ if (dsi_pll_res->vco_delay)
+ udelay(dsi_pll_res->vco_delay);
+
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_REFCLK_CFG, (u32)refclk_cfg);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_PWRGEN_CFG, 0x00);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_VCOLPF_CFG, 0x71);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG0, (u32)sdm_cfg0);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x12);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG6, 0x30);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG7, 0x00);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG8, 0x60);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG9, 0x00);
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG10, (u32)(cal_cfg10 & 0xff));
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG11, (u32)(cal_cfg11 & 0xff));
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_EFUSE_CFG, 0x20);
+
+ return 0;
+}
+
+unsigned long vco_get_rate(struct clk *c)
+{
+ u32 sdm0, doubler, sdm_byp_div;
+ u64 vco_rate;
+ u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ u64 ref_clk = vco->ref_clk_rate;
+ int rc;
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ if (is_gdsc_disabled(dsi_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ /* Check to see if the ref clk doubler is enabled */
+ doubler = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_REFCLK_CFG) & BIT(0);
+ ref_clk += (doubler * vco->ref_clk_rate);
+
+ /* see if it is integer mode or sdm mode */
+ sdm0 = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG0);
+ if (sdm0 & BIT(6)) {
+ /* integer mode */
+ sdm_byp_div = (MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG0) & 0x3f) + 1;
+ vco_rate = ref_clk * sdm_byp_div;
+ } else {
+ /* sdm mode */
+ sdm_dc_off = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG1) & 0xFF;
+ pr_debug("sdm_dc_off = %d\n", sdm_dc_off);
+ sdm2 = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG2) & 0xFF;
+ sdm3 = MDSS_PLL_REG_R(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_SDM_CFG3) & 0xFF;
+ sdm_freq_seed = (sdm3 << 8) | sdm2;
+ pr_debug("sdm_freq_seed = %d\n", sdm_freq_seed);
+
+ vco_rate = (ref_clk * (sdm_dc_off + 1)) +
+ mult_frac(ref_clk, sdm_freq_seed, BIT(16));
+ pr_debug("vco rate = %lld", vco_rate);
+ }
+
+ pr_debug("returning vco rate = %lu\n", (unsigned long)vco_rate);
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+
+ return (unsigned long)vco_rate;
+}
+
+static int dsi_pll_enable(struct clk *c)
+{
+ int i, rc;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return rc;
+ }
+
+ /* Try all enable sequences until one succeeds */
+ for (i = 0; i < vco->pll_en_seq_cnt; i++) {
+ rc = vco->pll_enable_seqs[i](dsi_pll_res);
+ pr_debug("DSI PLL %s after sequence #%d\n",
+ rc ? "unlocked" : "locked", i + 1);
+ if (!rc)
+ break;
+ }
+
+ if (rc) {
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ pr_err("DSI PLL failed to lock\n");
+ }
+ dsi_pll_res->pll_on = true;
+
+ return rc;
+}
+
+static void dsi_pll_disable(struct clk *c)
+{
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ if (!dsi_pll_res->pll_on &&
+ mdss_pll_resource_enable(dsi_pll_res, true)) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return;
+ }
+
+ dsi_pll_res->handoff_resources = false;
+
+ MDSS_PLL_REG_W(dsi_pll_res->pll_base,
+ DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x00);
+
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ dsi_pll_res->pll_on = false;
+
+ pr_debug("DSI PLL Disabled\n");
+}
+
+long vco_round_rate(struct clk *c, unsigned long rate)
+{
+ unsigned long rrate = rate;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+
+ if (rate < vco->min_rate)
+ rrate = vco->min_rate;
+ if (rate > vco->max_rate)
+ rrate = vco->max_rate;
+
+ return rrate;
+}
+
+enum handoff vco_handoff(struct clk *c)
+{
+ int rc;
+ enum handoff ret = HANDOFF_DISABLED_CLK;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ if (is_gdsc_disabled(dsi_pll_res))
+ return HANDOFF_DISABLED_CLK;
+
+ rc = mdss_pll_resource_enable(dsi_pll_res, true);
+ if (rc) {
+ pr_err("Failed to enable mdss dsi pll resources\n");
+ return ret;
+ }
+
+ if (dsi_pll_lock_status(dsi_pll_res)) {
+ dsi_pll_res->handoff_resources = true;
+ dsi_pll_res->pll_on = true;
+ c->rate = vco_get_rate(c);
+ ret = HANDOFF_ENABLED_CLK;
+ } else {
+ mdss_pll_resource_enable(dsi_pll_res, false);
+ }
+
+ return ret;
+}
+
+int vco_prepare(struct clk *c)
+{
+ int rc = 0;
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ if (!dsi_pll_res) {
+ pr_err("Dsi pll resources are not available\n");
+ return -EINVAL;
+ }
+
+ if ((dsi_pll_res->vco_cached_rate != 0)
+ && (dsi_pll_res->vco_cached_rate == c->rate)) {
+ rc = c->ops->set_rate(c, dsi_pll_res->vco_cached_rate);
+ if (rc) {
+ pr_err("vco_set_rate failed. rc=%d\n", rc);
+ goto error;
+ }
+ }
+
+ rc = dsi_pll_enable(c);
+
+error:
+ return rc;
+}
+
+void vco_unprepare(struct clk *c)
+{
+ struct dsi_pll_vco_clk *vco = to_vco_clk(c);
+ struct mdss_pll_resources *dsi_pll_res = vco->priv;
+
+ if (!dsi_pll_res) {
+ pr_err("Dsi pll resources are not available\n");
+ return;
+ }
+
+ dsi_pll_res->vco_cached_rate = c->rate;
+ dsi_pll_disable(c);
+}
+
diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll.h b/drivers/clk/qcom/mdss/mdss-dsi-pll.h
new file mode 100644
index 0000000..67fcd4d
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-dsi-pll.h
@@ -0,0 +1,107 @@
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MDSS_DSI_PLL_H
+#define __MDSS_DSI_PLL_H
+
+#define MAX_DSI_PLL_EN_SEQS 10
+
+#define DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG (0x0020)
+#define DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2 (0x0064)
+#define DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG (0x0068)
+#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1 (0x0070)
+
+/* Register offsets for 20nm PHY PLL */
+#define MMSS_DSI_PHY_PLL_PLL_CNTRL (0x0014)
+#define MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN (0x002C)
+#define MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN (0x009C)
+
+struct lpfr_cfg {
+ unsigned long vco_rate;
+ u32 r;
+};
+
+struct dsi_pll_vco_clk {
+ unsigned long ref_clk_rate;
+ unsigned long min_rate;
+ unsigned long max_rate;
+ u32 pll_en_seq_cnt;
+ struct lpfr_cfg *lpfr_lut;
+ u32 lpfr_lut_size;
+ void *priv;
+
+ struct clk c;
+
+ int (*pll_enable_seqs[MAX_DSI_PLL_EN_SEQS])
+ (struct mdss_pll_resources *dsi_pll_Res);
+};
+
+static inline struct dsi_pll_vco_clk *to_vco_clk(struct clk *clk)
+{
+ return container_of(clk, struct dsi_pll_vco_clk, c);
+}
+
+int dsi_pll_clock_register_hpm(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res);
+int dsi_pll_clock_register_20nm(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res);
+int dsi_pll_clock_register_lpm(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res);
+
+int set_byte_mux_sel(struct mux_clk *clk, int sel);
+int get_byte_mux_sel(struct mux_clk *clk);
+int dsi_pll_div_prepare(struct clk *c);
+int dsi_pll_mux_prepare(struct clk *c);
+int fixed_4div_set_div(struct div_clk *clk, int div);
+int fixed_4div_get_div(struct div_clk *clk);
+int digital_set_div(struct div_clk *clk, int div);
+int digital_get_div(struct div_clk *clk);
+int analog_set_div(struct div_clk *clk, int div);
+int analog_get_div(struct div_clk *clk);
+int dsi_pll_lock_status(struct mdss_pll_resources *dsi_pll_res);
+int vco_set_rate(struct dsi_pll_vco_clk *vco, unsigned long rate);
+unsigned long vco_get_rate(struct clk *c);
+long vco_round_rate(struct clk *c, unsigned long rate);
+enum handoff vco_handoff(struct clk *c);
+int vco_prepare(struct clk *c);
+void vco_unprepare(struct clk *c);
+
+/* APIs for 20nm PHY PLL */
+int pll_20nm_vco_set_rate(struct dsi_pll_vco_clk *vco, unsigned long rate);
+int shadow_pll_20nm_vco_set_rate(struct dsi_pll_vco_clk *vco,
+ unsigned long rate);
+long pll_20nm_vco_round_rate(struct clk *c, unsigned long rate);
+enum handoff pll_20nm_vco_handoff(struct clk *c);
+int pll_20nm_vco_prepare(struct clk *c);
+void pll_20nm_vco_unprepare(struct clk *c);
+int pll_20nm_vco_enable_seq(struct mdss_pll_resources *dsi_pll_res);
+
+int set_bypass_lp_div_mux_sel(struct mux_clk *clk, int sel);
+int set_shadow_bypass_lp_div_mux_sel(struct mux_clk *clk, int sel);
+int get_bypass_lp_div_mux_sel(struct mux_clk *clk);
+int fixed_hr_oclk2_set_div(struct div_clk *clk, int div);
+int shadow_fixed_hr_oclk2_set_div(struct div_clk *clk, int div);
+int fixed_hr_oclk2_get_div(struct div_clk *clk);
+int hr_oclk3_set_div(struct div_clk *clk, int div);
+int shadow_hr_oclk3_set_div(struct div_clk *clk, int div);
+int hr_oclk3_get_div(struct div_clk *clk);
+int ndiv_set_div(struct div_clk *clk, int div);
+int shadow_ndiv_set_div(struct div_clk *clk, int div);
+int ndiv_get_div(struct div_clk *clk);
+void __dsi_pll_disable(void __iomem *pll_base);
+
+int set_mdss_pixel_mux_sel(struct mux_clk *clk, int sel);
+int get_mdss_pixel_mux_sel(struct mux_clk *clk);
+int set_mdss_byte_mux_sel(struct mux_clk *clk, int sel);
+int get_mdss_byte_mux_sel(struct mux_clk *clk);
+
+#endif
diff --git a/drivers/clk/qcom/mdss/mdss-edp-pll-28hpm.c b/drivers/clk/qcom/mdss/mdss-edp-pll-28hpm.c
new file mode 100644
index 0000000..da3536d
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-edp-pll-28hpm.c
@@ -0,0 +1,593 @@
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/iopoll.h>
+#include <linux/clk/msm-clk-provider.h>
+#include <linux/clk/msm-clk.h>
+#include <linux/clk/msm-clock-generic.h>
+
+#include <dt-bindings/clock/msm-clocks-8974.h>
+
+#include "mdss-pll.h"
+#include "mdss-edp-pll.h"
+
+#define EDP_PHY_PLL_UNIPHY_PLL_REFCLK_CFG (0x0)
+#define EDP_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG (0x0004)
+#define EDP_PHY_PLL_UNIPHY_PLL_VCOLPF_CFG (0x000C)
+#define EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG (0x0020)
+#define EDP_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG (0x0024)
+#define EDP_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG (0x0028)
+#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG0 (0x0038)
+#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG1 (0x003C)
+#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG2 (0x0040)
+#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG3 (0x0044)
+#define EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG4 (0x0048)
+#define EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG0 (0x004C)
+#define EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG1 (0x0050)
+#define EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG2 (0x0054)
+#define EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG3 (0x0058)
+#define EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG2 (0x0064)
+#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG0 (0x006C)
+#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG2 (0x0074)
+#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG6 (0x0084)
+#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG7 (0x0088)
+#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG8 (0x008C)
+#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG9 (0x0090)
+#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG10 (0x0094)
+#define EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG11 (0x0098)
+#define EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG0 (0x005C)
+#define EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG1 (0x0060)
+
+#define EDP_PLL_POLL_MAX_READS 10
+#define EDP_PLL_POLL_TIMEOUT_US 50
+
+static const struct clk_ops edp_mainlink_clk_src_ops;
+static struct clk_div_ops fixed_5div_ops; /* null ops */
+static const struct clk_ops edp_pixel_clk_ops;
+
+static inline struct edp_pll_vco_clk *to_edp_vco_clk(struct clk *clk)
+{
+ return container_of(clk, struct edp_pll_vco_clk, c);
+}
+
+int edp_div_prepare(struct clk *c)
+{
+ struct div_clk *div = to_div_clk(c);
+ /* Restore the divider's value */
+ return div->ops->set_div(div, div->data.div);
+}
+
+static int edp_vco_set_rate(struct clk *c, unsigned long vco_rate)
+{
+ struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
+ struct mdss_pll_resources *edp_pll_res = vco->priv;
+ int rc;
+
+ pr_debug("vco_rate=%d\n", (int)vco_rate);
+
+ rc = mdss_pll_resource_enable(edp_pll_res, true);
+ if (rc) {
+ pr_err("failed to enable edp pll res rc=%d\n", rc);
+ rc = -EINVAL;
+ }
+
+ if (vco_rate == 810000000) {
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_VCOLPF_CFG, 0x18);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_REFCLK_CFG, 0x00);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG0, 0x36);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG1, 0x69);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG2, 0xff);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG3, 0x2f);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG4, 0x00);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG0, 0x80);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG1, 0x00);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG2, 0x00);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG3, 0x00);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x12);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG2, 0x01);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG6, 0x5a);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG7, 0x0);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG8, 0x60);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG9, 0x0);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG10, 0x2a);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG11, 0x3);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG0, 0x10);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG1, 0x1a);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG, 0x00);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG, 0x00);
+ } else if (vco_rate == 1350000000) {
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x0d);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_REFCLK_CFG, 0x01);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG0, 0x36);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG1, 0x62);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG2, 0x00);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG3, 0x28);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SDM_CFG4, 0x00);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG0, 0x80);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG1, 0x00);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG2, 0x00);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_SSC_CFG3, 0x00);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG0, 0x12);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG2, 0x01);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG6, 0x5a);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG7, 0x0);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG8, 0x60);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG9, 0x0);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG10, 0x46);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_CAL_CFG11, 0x5);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG0, 0x10);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_LKDET_CFG1, 0x1a);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG, 0x00);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG, 0x00);
+ } else {
+ pr_err("rate=%d is NOT supported\n", (int)vco_rate);
+ vco_rate = 0;
+ rc = -EINVAL;
+ }
+
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
+ udelay(100);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
+ udelay(100);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07);
+ udelay(100);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
+ udelay(100);
+ mdss_pll_resource_enable(edp_pll_res, false);
+
+ vco->rate = vco_rate;
+
+ return rc;
+}
+
+static int edp_pll_ready_poll(struct mdss_pll_resources *edp_pll_res)
+{
+ int cnt;
+ u32 status;
+
+ cnt = 100;
+ while (cnt--) {
+ udelay(100);
+ status = MDSS_PLL_REG_R(edp_pll_res->pll_base, 0xc0);
+ status &= 0x01;
+ if (status)
+ break;
+ }
+ pr_debug("cnt=%d status=%d\n", cnt, (int)status);
+
+ if (status)
+ return 1;
+
+ return 0;
+}
+
+static int edp_vco_enable(struct clk *c)
+{
+ int i, ready;
+ int rc;
+ struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
+ struct mdss_pll_resources *edp_pll_res = vco->priv;
+
+ rc = mdss_pll_resource_enable(edp_pll_res, true);
+ if (rc) {
+ pr_err("edp pll resources not available\n");
+ return rc;
+ }
+
+ for (i = 0; i < 3; i++) {
+ ready = edp_pll_ready_poll(edp_pll_res);
+ if (ready)
+ break;
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
+ udelay(100);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
+ udelay(100);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07);
+ udelay(100);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
+ udelay(100);
+ }
+
+ if (ready) {
+ pr_debug("EDP PLL lock success\n");
+ edp_pll_res->pll_on = true;
+ rc = 0;
+ } else {
+ pr_err("EDP PLL failed to lock\n");
+ mdss_pll_resource_enable(edp_pll_res, false);
+ rc = -EINVAL;
+ }
+
+ return rc;
+}
+
+static void edp_vco_disable(struct clk *c)
+{
+ struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
+ struct mdss_pll_resources *edp_pll_res = vco->priv;
+
+ if (!edp_pll_res) {
+ pr_err("Invalid input parameter\n");
+ return;
+ }
+
+ if (!edp_pll_res->pll_on &&
+ mdss_pll_resource_enable(edp_pll_res, true)) {
+ pr_err("edp pll resources not available\n");
+ return;
+ }
+
+ MDSS_PLL_REG_W(edp_pll_res->pll_base, 0x20, 0x00);
+
+ edp_pll_res->handoff_resources = false;
+ edp_pll_res->pll_on = false;
+
+ mdss_pll_resource_enable(edp_pll_res, false);
+
+ pr_debug("EDP PLL Disabled\n");
+}
+
+static unsigned long edp_vco_get_rate(struct clk *c)
+{
+ struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
+ struct mdss_pll_resources *edp_pll_res = vco->priv;
+ u32 pll_status, div2;
+ int rc;
+
+ if (is_gdsc_disabled(edp_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(edp_pll_res, true);
+ if (rc) {
+ pr_err("edp pll resources not available\n");
+ return rc;
+ }
+
+ if (vco->rate == 0) {
+ pll_status = MDSS_PLL_REG_R(edp_pll_res->pll_base, 0xc0);
+ if (pll_status & 0x01) {
+ div2 = MDSS_PLL_REG_R(edp_pll_res->pll_base, 0x24);
+ if (div2 & 0x01)
+ vco->rate = 1350000000;
+ else
+ vco->rate = 810000000;
+ }
+ }
+ mdss_pll_resource_enable(edp_pll_res, false);
+
+ pr_debug("rate=%d\n", (int)vco->rate);
+
+ return vco->rate;
+}
+
+static long edp_vco_round_rate(struct clk *c, unsigned long rate)
+{
+ struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
+ unsigned long rrate = -ENOENT;
+ unsigned long *lp;
+
+ lp = vco->rate_list;
+ while (*lp) {
+ rrate = *lp;
+ if (rate <= rrate)
+ break;
+ lp++;
+ }
+
+ pr_debug("rrate=%d\n", (int)rrate);
+
+ return rrate;
+}
+
+static int edp_vco_prepare(struct clk *c)
+{
+ struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
+
+ pr_debug("rate=%d\n", (int)vco->rate);
+
+ return edp_vco_set_rate(c, vco->rate);
+}
+
+static void edp_vco_unprepare(struct clk *c)
+{
+ struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
+
+ pr_debug("rate=%d\n", (int)vco->rate);
+
+ edp_vco_disable(c);
+}
+
+static int edp_pll_lock_status(struct mdss_pll_resources *edp_pll_res)
+{
+ u32 status;
+ int pll_locked = 0;
+ int rc;
+
+ rc = mdss_pll_resource_enable(edp_pll_res, true);
+ if (rc) {
+ pr_err("edp pll resources not available\n");
+ return rc;
+ }
+
+ /* poll for PLL ready status */
+ if (readl_poll_timeout_atomic((edp_pll_res->pll_base + 0xc0),
+ status, ((status & BIT(0)) == 1),
+ EDP_PLL_POLL_MAX_READS,
+ EDP_PLL_POLL_TIMEOUT_US)) {
+ pr_debug("EDP PLL status=%x failed to Lock\n", status);
+ pll_locked = 0;
+ } else {
+ pll_locked = 1;
+ }
+ mdss_pll_resource_enable(edp_pll_res, false);
+
+ return pll_locked;
+}
+
+static enum handoff edp_vco_handoff(struct clk *c)
+{
+ enum handoff ret = HANDOFF_DISABLED_CLK;
+ struct edp_pll_vco_clk *vco = to_edp_vco_clk(c);
+ struct mdss_pll_resources *edp_pll_res = vco->priv;
+
+ if (is_gdsc_disabled(edp_pll_res))
+ return HANDOFF_DISABLED_CLK;
+
+ if (mdss_pll_resource_enable(edp_pll_res, true)) {
+ pr_err("edp pll resources not available\n");
+ return ret;
+ }
+
+ edp_pll_res->handoff_resources = true;
+
+ if (edp_pll_lock_status(edp_pll_res)) {
+ c->rate = edp_vco_get_rate(c);
+ edp_pll_res->pll_on = true;
+ ret = HANDOFF_ENABLED_CLK;
+ } else {
+ edp_pll_res->handoff_resources = false;
+ mdss_pll_resource_enable(edp_pll_res, false);
+ }
+
+ pr_debug("done, ret=%d\n", ret);
+ return ret;
+}
+
+static unsigned long edp_vco_rate_list[] = {
+ 810000000, 1350000000, 0};
+
+struct const clk_ops edp_vco_clk_ops = {
+ .enable = edp_vco_enable,
+ .set_rate = edp_vco_set_rate,
+ .get_rate = edp_vco_get_rate,
+ .round_rate = edp_vco_round_rate,
+ .prepare = edp_vco_prepare,
+ .unprepare = edp_vco_unprepare,
+ .handoff = edp_vco_handoff,
+};
+
+struct edp_pll_vco_clk edp_vco_clk = {
+ .ref_clk_rate = 19200000,
+ .rate = 0,
+ .rate_list = edp_vco_rate_list,
+ .c = {
+ .dbg_name = "edp_vco_clk",
+ .ops = &edp_vco_clk_ops,
+ CLK_INIT(edp_vco_clk.c),
+ },
+};
+
+static unsigned long edp_mainlink_get_rate(struct clk *c)
+{
+ struct div_clk *mclk = to_div_clk(c);
+ struct clk *pclk;
+ unsigned long rate = 0;
+
+ pclk = clk_get_parent(c);
+
+ if (pclk && pclk->ops->get_rate) {
+ rate = pclk->ops->get_rate(pclk);
+ rate /= mclk->data.div;
+ }
+
+ pr_debug("rate=%d div=%d\n", (int)rate, mclk->data.div);
+
+ return rate;
+}
+
+
+struct div_clk edp_mainlink_clk_src = {
+ .ops = &fixed_5div_ops,
+ .data = {
+ .div = 5,
+ .min_div = 5,
+ .max_div = 5,
+ },
+ .c = {
+ .parent = &edp_vco_clk.c,
+ .dbg_name = "edp_mainlink_clk_src",
+ .ops = &edp_mainlink_clk_src_ops,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(edp_mainlink_clk_src.c),
+ }
+};
+
+/*
+ * this rate is from pll to clock controller
+ * output from pll to CC has two possibilities
+ * 1: if mainlink rate is 270M, then 675M
+ * 2: if mainlink rate is 162M, then 810M
+ */
+static int edp_pixel_set_div(struct div_clk *clk, int div)
+{
+ int rc;
+ struct mdss_pll_resources *edp_pll_res = clk->priv;
+
+ rc = mdss_pll_resource_enable(edp_pll_res, true);
+ if (rc) {
+ pr_err("edp pll resources not available\n");
+ return rc;
+ }
+
+ pr_debug("div=%d\n", div);
+ MDSS_PLL_REG_W(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG, (div - 1));
+ mdss_pll_resource_enable(edp_pll_res, false);
+
+ return 0;
+}
+
+static int edp_pixel_get_div(struct div_clk *clk)
+{
+ int div = 0;
+ int rc;
+ struct mdss_pll_resources *edp_pll_res = clk->priv;
+
+ if (is_gdsc_disabled(edp_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(edp_pll_res, true);
+ if (rc) {
+ pr_err("edp pll resources not available\n");
+ return rc;
+ }
+
+ div = MDSS_PLL_REG_R(edp_pll_res->pll_base,
+ EDP_PHY_PLL_UNIPHY_PLL_POSTDIV2_CFG);
+ mdss_pll_resource_enable(edp_pll_res, false);
+ div &= 0x01;
+ pr_debug("div=%d\n", div);
+ return div + 1;
+}
+
+static struct clk_div_ops edp_pixel_ops = {
+ .set_div = edp_pixel_set_div,
+ .get_div = edp_pixel_get_div,
+};
+
+struct div_clk edp_pixel_clk_src = {
+ .data = {
+ .max_div = 2,
+ .min_div = 1,
+ },
+ .ops = &edp_pixel_ops,
+ .c = {
+ .parent = &edp_vco_clk.c,
+ .dbg_name = "edp_pixel_clk_src",
+ .ops = &edp_pixel_clk_ops,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(edp_pixel_clk_src.c),
+ },
+};
+
+static struct clk_lookup mdss_edp_pllcc_8974[] = {
+ CLK_LOOKUP("edp_pixel_src", edp_pixel_clk_src.c,
+ "fd8c0000.qcom,mmsscc-mdss"),
+ CLK_LOOKUP("edp_mainlink_src", edp_mainlink_clk_src.c,
+ "fd8c0000.qcom,mmsscc-mdss"),
+};
+
+int edp_pll_clock_register(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ int rc = -ENOTSUPP;
+
+ if (!pll_res || !pll_res->pll_base) {
+ pr_err("Invalid input parameters\n");
+ return -EPROBE_DEFER;
+ }
+
+ /* Set client data to div and vco clocks */
+ edp_pixel_clk_src.priv = pll_res;
+ edp_mainlink_clk_src.priv = pll_res;
+ edp_vco_clk.priv = pll_res;
+
+ /* Set clock operation for mainlink and pixel clock */
+ edp_mainlink_clk_src_ops = clk_ops_div;
+ edp_mainlink_clk_src_ops.get_parent = clk_get_parent;
+ edp_mainlink_clk_src_ops.get_rate = edp_mainlink_get_rate;
+
+ edp_pixel_clk_ops = clk_ops_slave_div;
+ edp_pixel_clk_ops.prepare = edp_div_prepare;
+
+ rc = of_msm_clock_register(pdev->dev.of_node, mdss_edp_pllcc_8974,
+ ARRAY_SIZE(mdss_edp_pllcc_8974));
+ if (rc) {
+ pr_err("Clock register failed rc=%d\n", rc);
+ rc = -EPROBE_DEFER;
+ }
+
+ return rc;
+}
diff --git a/drivers/clk/qcom/mdss/mdss-edp-pll.h b/drivers/clk/qcom/mdss/mdss-edp-pll.h
new file mode 100644
index 0000000..c1f4f91
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-edp-pll.h
@@ -0,0 +1,27 @@
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MDSS_EDP_PLL_H
+#define __MDSS_EDP_PLL_H
+
+struct edp_pll_vco_clk {
+ unsigned long ref_clk_rate;
+ unsigned long rate; /* vco rate */
+ unsigned long *rate_list;
+ void *priv;
+
+ struct clk c;
+};
+
+int edp_pll_clock_register(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res);
+#endif
diff --git a/drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c b/drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c
new file mode 100644
index 0000000..40417f5
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-hdmi-pll-20nm.c
@@ -0,0 +1,983 @@
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <linux/clk/msm-clk-provider.h>
+#include <linux/clk/msm-clk.h>
+#include <linux/clk/msm-clock-generic.h>
+#include <dt-bindings/clock/msm-clocks-8994.h>
+
+#include "mdss-pll.h"
+#include "mdss-hdmi-pll.h"
+
+/* hdmi phy registers */
+
+#define HDMI_PHY_CMD_SIZE 68
+#define HDMI_PHY_CLK_SIZE 97
+
+/* Set to 1 for auto KVCO cal; set to 0 for fixed value */
+#define HDMI_PHY_AUTO_KVCO_CAL 1
+
+/* PLL REGISTERS */
+#define QSERDES_COM_SYS_CLK_CTRL (0x000)
+#define QSERDES_COM_PLL_VCOTAIL_EN (0x004)
+#define QSERDES_COM_CMN_MODE (0x008)
+#define QSERDES_COM_IE_TRIM (0x00C)
+#define QSERDES_COM_IP_TRIM (0x010)
+#define QSERDES_COM_PLL_CNTRL (0x014)
+#define QSERDES_COM_PLL_PHSEL_CONTROL (0x018)
+#define QSERDES_COM_IPTAT_TRIM_VCCA_TX_SEL (0x01C)
+#define QSERDES_COM_PLL_PHSEL_DC (0x020)
+#define QSERDES_COM_PLL_IP_SETI (0x024)
+#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL (0x028)
+#define QSERDES_COM_PLL_BKG_KVCO_CAL_EN (0x02C)
+#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN (0x030)
+#define QSERDES_COM_PLL_CP_SETI (0x034)
+#define QSERDES_COM_PLL_IP_SETP (0x038)
+#define QSERDES_COM_PLL_CP_SETP (0x03C)
+#define QSERDES_COM_ATB_SEL1 (0x040)
+#define QSERDES_COM_ATB_SEL2 (0x044)
+#define QSERDES_COM_SYSCLK_EN_SEL_TXBAND (0x048)
+#define QSERDES_COM_RESETSM_CNTRL (0x04C)
+#define QSERDES_COM_RESETSM_CNTRL2 (0x050)
+#define QSERDES_COM_RESETSM_CNTRL3 (0x054)
+#define QSERDES_COM_RESETSM_PLL_CAL_COUNT1 (0x058)
+#define QSERDES_COM_RESETSM_PLL_CAL_COUNT2 (0x05C)
+#define QSERDES_COM_DIV_REF1 (0x060)
+#define QSERDES_COM_DIV_REF2 (0x064)
+#define QSERDES_COM_KVCO_COUNT1 (0x068)
+#define QSERDES_COM_KVCO_COUNT2 (0x06C)
+#define QSERDES_COM_KVCO_CAL_CNTRL (0x070)
+#define QSERDES_COM_KVCO_CODE (0x074)
+#define QSERDES_COM_VREF_CFG1 (0x078)
+#define QSERDES_COM_VREF_CFG2 (0x07C)
+#define QSERDES_COM_VREF_CFG3 (0x080)
+#define QSERDES_COM_VREF_CFG4 (0x084)
+#define QSERDES_COM_VREF_CFG5 (0x088)
+#define QSERDES_COM_VREF_CFG6 (0x08C)
+#define QSERDES_COM_PLLLOCK_CMP1 (0x090)
+#define QSERDES_COM_PLLLOCK_CMP2 (0x094)
+#define QSERDES_COM_PLLLOCK_CMP3 (0x098)
+#define QSERDES_COM_PLLLOCK_CMP_EN (0x09C)
+#define QSERDES_COM_BGTC (0x0A0)
+#define QSERDES_COM_PLL_TEST_UPDN (0x0A4)
+#define QSERDES_COM_PLL_VCO_TUNE (0x0A8)
+#define QSERDES_COM_DEC_START1 (0x0AC)
+#define QSERDES_COM_PLL_AMP_OS (0x0B0)
+#define QSERDES_COM_SSC_EN_CENTER (0x0B4)
+#define QSERDES_COM_SSC_ADJ_PER1 (0x0B8)
+#define QSERDES_COM_SSC_ADJ_PER2 (0x0BC)
+#define QSERDES_COM_SSC_PER1 (0x0C0)
+#define QSERDES_COM_SSC_PER2 (0x0C4)
+#define QSERDES_COM_SSC_STEP_SIZE1 (0x0C8)
+#define QSERDES_COM_SSC_STEP_SIZE2 (0x0CC)
+#define QSERDES_COM_RES_CODE_UP (0x0D0)
+#define QSERDES_COM_RES_CODE_DN (0x0D4)
+#define QSERDES_COM_RES_CODE_UP_OFFSET (0x0D8)
+#define QSERDES_COM_RES_CODE_DN_OFFSET (0x0DC)
+#define QSERDES_COM_RES_CODE_START_SEG1 (0x0E0)
+#define QSERDES_COM_RES_CODE_START_SEG2 (0x0E4)
+#define QSERDES_COM_RES_CODE_CAL_CSR (0x0E8)
+#define QSERDES_COM_RES_CODE (0x0EC)
+#define QSERDES_COM_RES_TRIM_CONTROL (0x0F0)
+#define QSERDES_COM_RES_TRIM_CONTROL2 (0x0F4)
+#define QSERDES_COM_RES_TRIM_EN_VCOCALDONE (0x0F8)
+#define QSERDES_COM_FAUX_EN (0x0FC)
+#define QSERDES_COM_DIV_FRAC_START1 (0x100)
+#define QSERDES_COM_DIV_FRAC_START2 (0x104)
+#define QSERDES_COM_DIV_FRAC_START3 (0x108)
+#define QSERDES_COM_DEC_START2 (0x10C)
+#define QSERDES_COM_PLL_RXTXEPCLK_EN (0x110)
+#define QSERDES_COM_PLL_CRCTRL (0x114)
+#define QSERDES_COM_PLL_CLKEPDIV (0x118)
+#define QSERDES_COM_PLL_FREQUPDATE (0x11C)
+#define QSERDES_COM_PLL_BKGCAL_TRIM_UP (0x120)
+#define QSERDES_COM_PLL_BKGCAL_TRIM_DN (0x124)
+#define QSERDES_COM_PLL_BKGCAL_TRIM_MUX (0x128)
+#define QSERDES_COM_PLL_BKGCAL_VREF_CFG (0x12C)
+#define QSERDES_COM_PLL_BKGCAL_DIV_REF1 (0x130)
+#define QSERDES_COM_PLL_BKGCAL_DIV_REF2 (0x134)
+#define QSERDES_COM_MUXADDR (0x138)
+#define QSERDES_COM_LOW_POWER_RO_CONTROL (0x13C)
+#define QSERDES_COM_POST_DIVIDER_CONTROL (0x140)
+#define QSERDES_COM_HR_OCLK2_DIVIDER (0x144)
+#define QSERDES_COM_HR_OCLK3_DIVIDER (0x148)
+#define QSERDES_COM_PLL_VCO_HIGH (0x14C)
+#define QSERDES_COM_RESET_SM (0x150)
+#define QSERDES_COM_MUXVAL (0x154)
+#define QSERDES_COM_CORE_RES_CODE_DN (0x158)
+#define QSERDES_COM_CORE_RES_CODE_UP (0x15C)
+#define QSERDES_COM_CORE_VCO_TUNE (0x160)
+#define QSERDES_COM_CORE_VCO_TAIL (0x164)
+#define QSERDES_COM_CORE_KVCO_CODE (0x168)
+
+/* Tx Channel 0 REGISTERS */
+#define QSERDES_TX_L0_BIST_MODE_LANENO (0x00)
+#define QSERDES_TX_L0_CLKBUF_ENABLE (0x04)
+#define QSERDES_TX_L0_TX_EMP_POST1_LVL (0x08)
+#define QSERDES_TX_L0_TX_DRV_LVL (0x0C)
+#define QSERDES_TX_L0_RESET_TSYNC_EN (0x10)
+#define QSERDES_TX_L0_LPB_EN (0x14)
+#define QSERDES_TX_L0_RES_CODE_UP (0x18)
+#define QSERDES_TX_L0_RES_CODE_DN (0x1C)
+#define QSERDES_TX_L0_PERL_LENGTH1 (0x20)
+#define QSERDES_TX_L0_PERL_LENGTH2 (0x24)
+#define QSERDES_TX_L0_SERDES_BYP_EN_OUT (0x28)
+#define QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x2C)
+#define QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN (0x30)
+#define QSERDES_TX_L0_BIST_PATTERN1 (0x34)
+#define QSERDES_TX_L0_BIST_PATTERN2 (0x38)
+#define QSERDES_TX_L0_BIST_PATTERN3 (0x3C)
+#define QSERDES_TX_L0_BIST_PATTERN4 (0x40)
+#define QSERDES_TX_L0_BIST_PATTERN5 (0x44)
+#define QSERDES_TX_L0_BIST_PATTERN6 (0x48)
+#define QSERDES_TX_L0_BIST_PATTERN7 (0x4C)
+#define QSERDES_TX_L0_BIST_PATTERN8 (0x50)
+#define QSERDES_TX_L0_LANE_MODE (0x54)
+#define QSERDES_TX_L0_IDAC_CAL_LANE_MODE (0x58)
+#define QSERDES_TX_L0_IDAC_CAL_LANE_MODE_CONFIGURATION (0x5C)
+#define QSERDES_TX_L0_ATB_SEL1 (0x60)
+#define QSERDES_TX_L0_ATB_SEL2 (0x64)
+#define QSERDES_TX_L0_RCV_DETECT_LVL (0x68)
+#define QSERDES_TX_L0_PRBS_SEED1 (0x6C)
+#define QSERDES_TX_L0_PRBS_SEED2 (0x70)
+#define QSERDES_TX_L0_PRBS_SEED3 (0x74)
+#define QSERDES_TX_L0_PRBS_SEED4 (0x78)
+#define QSERDES_TX_L0_RESET_GEN (0x7C)
+#define QSERDES_TX_L0_TRAN_DRVR_EMP_EN (0x80)
+#define QSERDES_TX_L0_TX_INTERFACE_MODE (0x84)
+#define QSERDES_TX_L0_PWM_CTRL (0x88)
+#define QSERDES_TX_L0_PWM_DATA (0x8C)
+#define QSERDES_TX_L0_PWM_ENC_DIV_CTRL (0x90)
+#define QSERDES_TX_L0_VMODE_CTRL1 (0x94)
+#define QSERDES_TX_L0_VMODE_CTRL2 (0x98)
+#define QSERDES_TX_L0_VMODE_CTRL3 (0x9C)
+#define QSERDES_TX_L0_VMODE_CTRL4 (0xA0)
+#define QSERDES_TX_L0_VMODE_CTRL5 (0xA4)
+#define QSERDES_TX_L0_VMODE_CTRL6 (0xA8)
+#define QSERDES_TX_L0_VMODE_CTRL7 (0xAC)
+#define QSERDES_TX_L0_TX_ALOG_INTF_OBSV_CNTL (0xB0)
+#define QSERDES_TX_L0_BIST_STATUS (0xB4)
+#define QSERDES_TX_L0_BIST_ERROR_COUNT1 (0xB8)
+#define QSERDES_TX_L0_BIST_ERROR_COUNT2 (0xBC)
+#define QSERDES_TX_L0_TX_ALOG_INTF_OBSV (0xC0)
+#define QSERDES_TX_L0_PWM_DEC_STATUS (0xC4)
+
+/* Tx Channel 1 REGISTERS */
+#define QSERDES_TX_L1_BIST_MODE_LANENO (0x00)
+#define QSERDES_TX_L1_CLKBUF_ENABLE (0x04)
+#define QSERDES_TX_L1_TX_EMP_POST1_LVL (0x08)
+#define QSERDES_TX_L1_TX_DRV_LVL (0x0C)
+#define QSERDES_TX_L1_RESET_TSYNC_EN (0x10)
+#define QSERDES_TX_L1_LPB_EN (0x14)
+#define QSERDES_TX_L1_RES_CODE_UP (0x18)
+#define QSERDES_TX_L1_RES_CODE_DN (0x1C)
+#define QSERDES_TX_L1_PERL_LENGTH1 (0x20)
+#define QSERDES_TX_L1_PERL_LENGTH2 (0x24)
+#define QSERDES_TX_L1_SERDES_BYP_EN_OUT (0x28)
+#define QSERDES_TX_L1_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x2C)
+#define QSERDES_TX_L1_PARRATE_REC_DETECT_IDLE_EN (0x30)
+#define QSERDES_TX_L1_BIST_PATTERN1 (0x34)
+#define QSERDES_TX_L1_BIST_PATTERN2 (0x38)
+#define QSERDES_TX_L1_BIST_PATTERN3 (0x3C)
+#define QSERDES_TX_L1_BIST_PATTERN4 (0x40)
+#define QSERDES_TX_L1_BIST_PATTERN5 (0x44)
+#define QSERDES_TX_L1_BIST_PATTERN6 (0x48)
+#define QSERDES_TX_L1_BIST_PATTERN7 (0x4C)
+#define QSERDES_TX_L1_BIST_PATTERN8 (0x50)
+#define QSERDES_TX_L1_LANE_MODE (0x54)
+#define QSERDES_TX_L1_IDAC_CAL_LANE_MODE (0x58)
+#define QSERDES_TX_L1_IDAC_CAL_LANE_MODE_CONFIGURATION (0x5C)
+#define QSERDES_TX_L1_ATB_SEL1 (0x60)
+#define QSERDES_TX_L1_ATB_SEL2 (0x64)
+#define QSERDES_TX_L1_RCV_DETECT_LVL (0x68)
+#define QSERDES_TX_L1_PRBS_SEED1 (0x6C)
+#define QSERDES_TX_L1_PRBS_SEED2 (0x70)
+#define QSERDES_TX_L1_PRBS_SEED3 (0x74)
+#define QSERDES_TX_L1_PRBS_SEED4 (0x78)
+#define QSERDES_TX_L1_RESET_GEN (0x7C)
+#define QSERDES_TX_L1_TRAN_DRVR_EMP_EN (0x80)
+#define QSERDES_TX_L1_TX_INTERFACE_MODE (0x84)
+#define QSERDES_TX_L1_PWM_CTRL (0x88)
+#define QSERDES_TX_L1_PWM_DATA (0x8C)
+#define QSERDES_TX_L1_PWM_ENC_DIV_CTRL (0x90)
+#define QSERDES_TX_L1_VMODE_CTRL1 (0x94)
+#define QSERDES_TX_L1_VMODE_CTRL2 (0x98)
+#define QSERDES_TX_L1_VMODE_CTRL3 (0x9C)
+#define QSERDES_TX_L1_VMODE_CTRL4 (0xA0)
+#define QSERDES_TX_L1_VMODE_CTRL5 (0xA4)
+#define QSERDES_TX_L1_VMODE_CTRL6 (0xA8)
+#define QSERDES_TX_L1_VMODE_CTRL7 (0xAC)
+#define QSERDES_TX_L1_TX_ALOG_INTF_OBSV_CNTL (0xB0)
+#define QSERDES_TX_L1_BIST_STATUS (0xB4)
+#define QSERDES_TX_L1_BIST_ERROR_COUNT1 (0xB8)
+#define QSERDES_TX_L1_BIST_ERROR_COUNT2 (0xBC)
+#define QSERDES_TX_L1_TX_ALOG_INTF_OBSV (0xC0)
+#define QSERDES_TX_L1_PWM_DEC_STATUS (0xC4)
+
+/* Tx Channel 2 REGISERS */
+#define QSERDES_TX_L2_BIST_MODE_LANENO (0x00)
+#define QSERDES_TX_L2_CLKBUF_ENABLE (0x04)
+#define QSERDES_TX_L2_TX_EMP_POST1_LVL (0x08)
+#define QSERDES_TX_L2_TX_DRV_LVL (0x0C)
+#define QSERDES_TX_L2_RESET_TSYNC_EN (0x10)
+#define QSERDES_TX_L2_LPB_EN (0x14)
+#define QSERDES_TX_L2_RES_CODE_UP (0x18)
+#define QSERDES_TX_L2_RES_CODE_DN (0x1C)
+#define QSERDES_TX_L2_PERL_LENGTH1 (0x20)
+#define QSERDES_TX_L2_PERL_LENGTH2 (0x24)
+#define QSERDES_TX_L2_SERDES_BYP_EN_OUT (0x28)
+#define QSERDES_TX_L2_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x2C)
+#define QSERDES_TX_L2_PARRATE_REC_DETECT_IDLE_EN (0x30)
+#define QSERDES_TX_L2_BIST_PATTERN1 (0x34)
+#define QSERDES_TX_L2_BIST_PATTERN2 (0x38)
+#define QSERDES_TX_L2_BIST_PATTERN3 (0x3C)
+#define QSERDES_TX_L2_BIST_PATTERN4 (0x40)
+#define QSERDES_TX_L2_BIST_PATTERN5 (0x44)
+#define QSERDES_TX_L2_BIST_PATTERN6 (0x48)
+#define QSERDES_TX_L2_BIST_PATTERN7 (0x4C)
+#define QSERDES_TX_L2_BIST_PATTERN8 (0x50)
+#define QSERDES_TX_L2_LANE_MODE (0x54)
+#define QSERDES_TX_L2_IDAC_CAL_LANE_MODE (0x58)
+#define QSERDES_TX_L2_IDAC_CAL_LANE_MODE_CONFIGURATION (0x5C)
+#define QSERDES_TX_L2_ATB_SEL1 (0x60)
+#define QSERDES_TX_L2_ATB_SEL2 (0x64)
+#define QSERDES_TX_L2_RCV_DETECT_LVL (0x68)
+#define QSERDES_TX_L2_PRBS_SEED1 (0x6C)
+#define QSERDES_TX_L2_PRBS_SEED2 (0x70)
+#define QSERDES_TX_L2_PRBS_SEED3 (0x74)
+#define QSERDES_TX_L2_PRBS_SEED4 (0x78)
+#define QSERDES_TX_L2_RESET_GEN (0x7C)
+#define QSERDES_TX_L2_TRAN_DRVR_EMP_EN (0x80)
+#define QSERDES_TX_L2_TX_INTERFACE_MODE (0x84)
+#define QSERDES_TX_L2_PWM_CTRL (0x88)
+#define QSERDES_TX_L2_PWM_DATA (0x8C)
+#define QSERDES_TX_L2_PWM_ENC_DIV_CTRL (0x90)
+#define QSERDES_TX_L2_VMODE_CTRL1 (0x94)
+#define QSERDES_TX_L2_VMODE_CTRL2 (0x98)
+#define QSERDES_TX_L2_VMODE_CTRL3 (0x9C)
+#define QSERDES_TX_L2_VMODE_CTRL4 (0xA0)
+#define QSERDES_TX_L2_VMODE_CTRL5 (0xA4)
+#define QSERDES_TX_L2_VMODE_CTRL6 (0xA8)
+#define QSERDES_TX_L2_VMODE_CTRL7 (0xAC)
+#define QSERDES_TX_L2_TX_ALOG_INTF_OBSV_CNTL (0xB0)
+#define QSERDES_TX_L2_BIST_STATUS (0xB4)
+#define QSERDES_TX_L2_BIST_ERROR_COUNT1 (0xB8)
+#define QSERDES_TX_L2_BIST_ERROR_COUNT2 (0xBC)
+#define QSERDES_TX_L2_TX_ALOG_INTF_OBSV (0xC0)
+#define QSERDES_TX_L2_PWM_DEC_STATUS (0xC4)
+
+/* Tx Channel 3 REGISERS */
+#define QSERDES_TX_L3_BIST_MODE_LANENO (0x00)
+#define QSERDES_TX_L3_CLKBUF_ENABLE (0x04)
+#define QSERDES_TX_L3_TX_EMP_POST1_LVL (0x08)
+#define QSERDES_TX_L3_TX_DRV_LVL (0x0C)
+#define QSERDES_TX_L3_RESET_TSYNC_EN (0x10)
+#define QSERDES_TX_L3_LPB_EN (0x14)
+#define QSERDES_TX_L3_RES_CODE_UP (0x18)
+#define QSERDES_TX_L3_RES_CODE_DN (0x1C)
+#define QSERDES_TX_L3_PERL_LENGTH1 (0x20)
+#define QSERDES_TX_L3_PERL_LENGTH2 (0x24)
+#define QSERDES_TX_L3_SERDES_BYP_EN_OUT (0x28)
+#define QSERDES_TX_L3_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN (0x2C)
+#define QSERDES_TX_L3_PARRATE_REC_DETECT_IDLE_EN (0x30)
+#define QSERDES_TX_L3_BIST_PATTERN1 (0x34)
+#define QSERDES_TX_L3_BIST_PATTERN2 (0x38)
+#define QSERDES_TX_L3_BIST_PATTERN3 (0x3C)
+#define QSERDES_TX_L3_BIST_PATTERN4 (0x40)
+#define QSERDES_TX_L3_BIST_PATTERN5 (0x44)
+#define QSERDES_TX_L3_BIST_PATTERN6 (0x48)
+#define QSERDES_TX_L3_BIST_PATTERN7 (0x4C)
+#define QSERDES_TX_L3_BIST_PATTERN8 (0x50)
+#define QSERDES_TX_L3_LANE_MODE (0x54)
+#define QSERDES_TX_L3_IDAC_CAL_LANE_MODE (0x58)
+#define QSERDES_TX_L3_IDAC_CAL_LANE_MODE_CONFIGURATION (0x5C)
+#define QSERDES_TX_L3_ATB_SEL1 (0x60)
+#define QSERDES_TX_L3_ATB_SEL2 (0x64)
+#define QSERDES_TX_L3_RCV_DETECT_LVL (0x68)
+#define QSERDES_TX_L3_PRBS_SEED1 (0x6C)
+#define QSERDES_TX_L3_PRBS_SEED2 (0x70)
+#define QSERDES_TX_L3_PRBS_SEED3 (0x74)
+#define QSERDES_TX_L3_PRBS_SEED4 (0x78)
+#define QSERDES_TX_L3_RESET_GEN (0x7C)
+#define QSERDES_TX_L3_TRAN_DRVR_EMP_EN (0x80)
+#define QSERDES_TX_L3_TX_INTERFACE_MODE (0x84)
+#define QSERDES_TX_L3_PWM_CTRL (0x88)
+#define QSERDES_TX_L3_PWM_DATA (0x8C)
+#define QSERDES_TX_L3_PWM_ENC_DIV_CTRL (0x90)
+#define QSERDES_TX_L3_VMODE_CTRL1 (0x94)
+#define QSERDES_TX_L3_VMODE_CTRL2 (0x98)
+#define QSERDES_TX_L3_VMODE_CTRL3 (0x9C)
+#define QSERDES_TX_L3_VMODE_CTRL4 (0xA0)
+#define QSERDES_TX_L3_VMODE_CTRL5 (0xA4)
+#define QSERDES_TX_L3_VMODE_CTRL6 (0xA8)
+#define QSERDES_TX_L3_VMODE_CTRL7 (0xAC)
+#define QSERDES_TX_L3_TX_ALOG_INTF_OBSV_CNTL (0xB0)
+#define QSERDES_TX_L3_BIST_STATUS (0xB4)
+#define QSERDES_TX_L3_BIST_ERROR_COUNT1 (0xB8)
+#define QSERDES_TX_L3_BIST_ERROR_COUNT2 (0xBC)
+#define QSERDES_TX_L3_TX_ALOG_INTF_OBSV (0xC0)
+#define QSERDES_TX_L3_PWM_DEC_STATUS (0xC4)
+
+/* HDMI PHY REGISTERS */
+#define HDMI_PHY_CFG (0x00)
+#define HDMI_PHY_PD_CTL (0x04)
+#define HDMI_PHY_MODE (0x08)
+#define HDMI_PHY_MISR_CLEAR (0x0C)
+#define HDMI_PHY_TX0_TX1_BIST_CFG0 (0x10)
+#define HDMI_PHY_TX0_TX1_BIST_CFG1 (0x14)
+#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE0 (0x18)
+#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE1 (0x1C)
+#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE2 (0x20)
+#define HDMI_PHY_TX0_TX1_PRBS_SEED_BYTE3 (0x24)
+#define HDMI_PHY_TX0_TX1_PRBS_POLY_BYTE0 (0x28)
+#define HDMI_PHY_TX0_TX1_PRBS_POLY_BYTE1 (0x2C)
+#define HDMI_PHY_TX0_TX1_PRBS_POLY_BYTE2 (0x30)
+#define HDMI_PHY_TX0_TX1_PRBS_POLY_BYTE3 (0x34)
+#define HDMI_PHY_TX2_TX3_BIST_CFG0 (0x38)
+#define HDMI_PHY_TX2_TX3_BIST_CFG1 (0x3C)
+#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE0 (0x40)
+#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE1 (0x44)
+#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE2 (0x48)
+#define HDMI_PHY_TX2_TX3_PRBS_SEED_BYTE3 (0x4C)
+#define HDMI_PHY_TX2_TX3_PRBS_POLY_BYTE0 (0x50)
+#define HDMI_PHY_TX2_TX3_PRBS_POLY_BYTE1 (0x54)
+#define HDMI_PHY_TX2_TX3_PRBS_POLY_BYTE2 (0x58)
+#define HDMI_PHY_TX2_TX3_PRBS_POLY_BYTE3 (0x5C)
+#define HDMI_PHY_DEBUG_BUS_SEL (0x60)
+#define HDMI_PHY_TXCAL_CFG0 (0x64)
+#define HDMI_PHY_TXCAL_CFG1 (0x68)
+#define HDMI_PHY_TX0_TX1_BIST_STATUS0 (0x6C)
+#define HDMI_PHY_TX0_TX1_BIST_STATUS1 (0x70)
+#define HDMI_PHY_TX0_TX1_BIST_STATUS2 (0x74)
+#define HDMI_PHY_TX2_TX3_BIST_STATUS0 (0x78)
+#define HDMI_PHY_TX2_TX3_BIST_STATUS1 (0x7C)
+#define HDMI_PHY_TX2_TX3_BIST_STATUS2 (0x80)
+#define HDMI_PHY_PRE_MISR_STATUS0 (0x84)
+#define HDMI_PHY_PRE_MISR_STATUS1 (0x88)
+#define HDMI_PHY_PRE_MISR_STATUS2 (0x8C)
+#define HDMI_PHY_PRE_MISR_STATUS3 (0x90)
+#define HDMI_PHY_POST_MISR_STATUS0 (0x94)
+#define HDMI_PHY_POST_MISR_STATUS1 (0x98)
+#define HDMI_PHY_POST_MISR_STATUS2 (0x9C)
+#define HDMI_PHY_POST_MISR_STATUS3 (0xA0)
+#define HDMI_PHY_STATUS (0xA4)
+#define HDMI_PHY_MISC3_STATUS (0xA8)
+#define HDMI_PHY_DEBUG_BUS0 (0xAC)
+#define HDMI_PHY_DEBUG_BUS1 (0xB0)
+#define HDMI_PHY_DEBUG_BUS2 (0xB4)
+#define HDMI_PHY_DEBUG_BUS3 (0xB8)
+#define HDMI_PHY_REVISION_ID0 (0xBC)
+#define HDMI_PHY_REVISION_ID1 (0xC0)
+#define HDMI_PHY_REVISION_ID2 (0xC4)
+#define HDMI_PHY_REVISION_ID3 (0xC8)
+
+#define HDMI_PLL_POLL_MAX_READS 2500
+#define HDMI_PLL_POLL_TIMEOUT_US 50
+#define HDMI_PLL_REF_CLK_RATE 192ULL
+#define HDMI_PLL_DIVISOR 10000000000ULL
+#define HDMI_PLL_DIVISOR_32 100000U
+#define HDMI_PLL_MIN_VCO_CLK 160000000ULL
+#define HDMI_PLL_TMDS_MAX 800000000U
+
+
+static int hdmi_20nm_pll_lock_status(struct mdss_pll_resources *io)
+{
+ u32 status;
+ int pll_locked = 0;
+ int phy_ready = 0;
+ int rc;
+
+ rc = mdss_pll_resource_enable(io, true);
+ if (rc) {
+ pr_err("pll resource can't be enabled\n");
+ return rc;
+ }
+
+ /* Poll for C_READY and PHY READY */
+ pr_debug("%s: Waiting for PHY Ready\n", __func__);
+
+ /* poll for PLL ready status */
+ if (!readl_poll_timeout_atomic(
+ (io->pll_base + QSERDES_COM_RESET_SM),
+ status, ((status & BIT(6)) == 1),
+ HDMI_PLL_POLL_MAX_READS,
+ HDMI_PLL_POLL_TIMEOUT_US)) {
+ pr_debug("%s: C READY\n", __func__);
+ pll_locked = 1;
+ } else {
+ pr_debug("%s: C READY TIMEOUT\n", __func__);
+ pll_locked = 0;
+ }
+
+ /* poll for PHY ready status */
+ if (pll_locked && !readl_poll_timeout_atomic(
+ (io->phy_base + HDMI_PHY_STATUS),
+ status, ((status & BIT(0)) == 1),
+ HDMI_PLL_POLL_MAX_READS,
+ HDMI_PLL_POLL_TIMEOUT_US)) {
+ pr_debug("%s: PHY READY\n", __func__);
+ phy_ready = 1;
+ } else {
+ pr_debug("%s: PHY READY TIMEOUT\n", __func__);
+ phy_ready = 0;
+ }
+ mdss_pll_resource_enable(io, false);
+
+ return phy_ready;
+}
+
+static inline struct hdmi_pll_vco_clk *to_hdmi_20nm_vco_clk(struct clk *clk)
+{
+ return container_of(clk, struct hdmi_pll_vco_clk, c);
+}
+
+static inline u32 hdmi_20nm_phy_pll_vco_reg_val(struct hdmi_pll_cfg *pll_cfg,
+ u32 tmds_clk)
+{
+ u32 index = 0;
+
+ while (pll_cfg[index].vco_rate < HDMI_PLL_TMDS_MAX &&
+ pll_cfg[index].vco_rate < tmds_clk)
+ index++;
+ return pll_cfg[index].reg;
+}
+
+static void hdmi_20nm_phy_pll_calc_settings(struct mdss_pll_resources *io,
+ struct hdmi_pll_vco_clk *vco, u32 vco_clk, u32 tmds_clk)
+{
+ u32 val = 0;
+ u64 dec_start_val, frac_start_val, pll_lock_cmp;
+
+ /* Calculate decimal and fractional values */
+ dec_start_val = 1000000UL * vco_clk;
+ do_div(dec_start_val, HDMI_PLL_REF_CLK_RATE);
+ do_div(dec_start_val, 2U);
+ frac_start_val = dec_start_val;
+ do_div(frac_start_val, HDMI_PLL_DIVISOR_32);
+ do_div(frac_start_val, HDMI_PLL_DIVISOR_32);
+ frac_start_val *= HDMI_PLL_DIVISOR;
+ frac_start_val = dec_start_val - frac_start_val;
+ frac_start_val *= (u64)(2 << 19);
+ do_div(frac_start_val, HDMI_PLL_DIVISOR_32);
+ do_div(frac_start_val, HDMI_PLL_DIVISOR_32);
+ pll_lock_cmp = dec_start_val;
+ do_div(pll_lock_cmp, 10U);
+ pll_lock_cmp *= 0x800;
+ do_div(pll_lock_cmp, HDMI_PLL_DIVISOR_32);
+ do_div(pll_lock_cmp, HDMI_PLL_DIVISOR_32);
+ pll_lock_cmp -= 1U;
+ do_div(dec_start_val, HDMI_PLL_DIVISOR_32);
+ do_div(dec_start_val, HDMI_PLL_DIVISOR_32);
+
+ /* PLL loop bandwidth */
+ val = hdmi_20nm_phy_pll_vco_reg_val(vco->ip_seti, tmds_clk);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_IP_SETI, val);
+ val = hdmi_20nm_phy_pll_vco_reg_val(vco->cp_seti, tmds_clk);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CP_SETI, val);
+ val = hdmi_20nm_phy_pll_vco_reg_val(vco->cp_setp, tmds_clk);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CP_SETP, val);
+ val = hdmi_20nm_phy_pll_vco_reg_val(vco->ip_setp, tmds_clk);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_IP_SETP, val);
+ val = hdmi_20nm_phy_pll_vco_reg_val(vco->crctrl, tmds_clk);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CRCTRL, val);
+
+ /* PLL calibration */
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START1,
+ 0x80 | (frac_start_val & 0x7F));
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START2,
+ 0x80 | ((frac_start_val >> 7) & 0x7F));
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_FRAC_START3,
+ 0x40 | ((frac_start_val >> 14) & 0x3F));
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEC_START1,
+ 0x80 | (dec_start_val & 0x7F));
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DEC_START2,
+ 0x02 | (0x01 & (dec_start_val >> 7)));
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP1,
+ pll_lock_cmp & 0xFF);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP2,
+ (pll_lock_cmp >> 8) & 0xFF);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP3,
+ (pll_lock_cmp >> 16) & 0xFF);
+}
+
+static u32 hdmi_20nm_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk)
+{
+ u32 tx_band = 0;
+
+ struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
+ struct mdss_pll_resources *io = vco->priv;
+ u64 vco_clk = tmds_clk;
+
+ while (vco_clk > 0 && vco_clk < HDMI_PLL_MIN_VCO_CLK) {
+ tx_band++;
+ vco_clk *= 2;
+ }
+
+ /* Initially shut down PHY */
+ pr_debug("%s: Disabling PHY\n", __func__);
+ MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_PD_CTL, 0x0);
+ udelay(1000);
+ /* memory barrier */
+ mb();
+
+ /* power-up and recommended common block settings */
+ MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_PD_CTL, 0x1F);
+ MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x01);
+ udelay(1000);
+ /* memory barrier */
+ mb();
+
+ MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x07);
+ udelay(1000);
+ /* memory barrier */
+ mb();
+
+ MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x05);
+ udelay(1000);
+ /* memory barrier */
+ mb();
+
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SYS_CLK_CTRL, 0x42);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_VCOTAIL_EN, 0x03);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CMN_MODE, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_IE_TRIM, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_IP_TRIM, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CNTRL, 0x07);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_PHSEL_CONTROL, 0x04);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_IPTAT_TRIM_VCCA_TX_SEL, 0xA0);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_PHSEL_DC, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_CORE_CLK_IN_SYNC_SEL, 0x00);
+
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_BKG_KVCO_CAL_EN, 0x00);
+
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x0F);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_ATB_SEL1, 0x01);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_ATB_SEL2, 0x01);
+
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SYSCLK_EN_SEL_TXBAND,
+ 0x4A + (0x10 * tx_band));
+
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG1, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG2, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_BGTC, 0xFF);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_TEST_UPDN, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_VCO_TUNE, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_AMP_OS, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_EN_CENTER, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_CODE_UP, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_CODE_DN, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_KVCO_CODE,
+ tmds_clk > 300000000 ? 0x3F : 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_KVCO_COUNT1,
+ tmds_clk > 300000000 ? 0x00 : 0x8A);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_REF1, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_DIV_REF2,
+ tmds_clk > 300000000 ? 0x00 : 0x01);
+
+
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_KVCO_CAL_CNTRL,
+ tmds_clk > 300000000 ? 0x00 : 0x1F);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG3,
+ tmds_clk > 300000000 ? 0x00 : 0x40);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG4, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_VREF_CFG5, 0x10);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RESETSM_CNTRL,
+ tmds_clk > 300000000 ? 0x80 : 0x00);
+
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_CODE_CAL_CSR, 0x77);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_TRIM_EN_VCOCALDONE, 0x00);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_RXTXEPCLK_EN, 0x0C);
+
+ hdmi_20nm_phy_pll_calc_settings(io, vco, vco_clk, tmds_clk);
+
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLLLOCK_CMP_EN, 0x11);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_PLL_CNTRL, 0x07);
+
+ /* Resistor calibration linear search */
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_CODE_START_SEG1, 0x60);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_CODE_START_SEG2, 0x60);
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RES_TRIM_CONTROL, 0x01);
+
+ MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_RESETSM_CNTRL2, 0x07);
+
+ udelay(1000);
+ /* memory barrier */
+ mb();
+
+ MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_MODE, tx_band);
+
+ /* TX lanes (transceivers) power-up sequence */
+ MDSS_PLL_REG_W(io->pll_base + 0x400, QSERDES_TX_L0_CLKBUF_ENABLE, 0x03);
+ MDSS_PLL_REG_W(io->pll_base + 0x600, QSERDES_TX_L1_CLKBUF_ENABLE, 0x03);
+ MDSS_PLL_REG_W(io->pll_base + 0x800, QSERDES_TX_L2_CLKBUF_ENABLE, 0x03);
+ MDSS_PLL_REG_W(io->pll_base + 0xA00, QSERDES_TX_L3_CLKBUF_ENABLE, 0x03);
+
+ MDSS_PLL_REG_W(io->pll_base + 0x400,
+ QSERDES_TX_L0_TRAN_DRVR_EMP_EN, 0x03);
+ MDSS_PLL_REG_W(io->pll_base + 0x600,
+ QSERDES_TX_L1_TRAN_DRVR_EMP_EN, 0x03);
+ MDSS_PLL_REG_W(io->pll_base + 0x800,
+ QSERDES_TX_L2_TRAN_DRVR_EMP_EN, 0x03);
+ MDSS_PLL_REG_W(io->pll_base + 0xA00,
+ QSERDES_TX_L3_TRAN_DRVR_EMP_EN, 0x03);
+
+ MDSS_PLL_REG_W(io->pll_base + 0x400,
+ QSERDES_TX_L0_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x6F);
+ MDSS_PLL_REG_W(io->pll_base + 0x600,
+ QSERDES_TX_L1_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x6F);
+ MDSS_PLL_REG_W(io->pll_base + 0x800,
+ QSERDES_TX_L2_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x6F);
+ MDSS_PLL_REG_W(io->pll_base + 0xA00,
+ QSERDES_TX_L3_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x6F);
+
+ MDSS_PLL_REG_W(io->pll_base + 0x400,
+ QSERDES_TX_L0_TX_EMP_POST1_LVL, 0x0000002F);
+ MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_TXCAL_CFG0, 0x000000AF);
+
+ MDSS_PLL_REG_W(io->pll_base + 0x400, QSERDES_TX_L0_VMODE_CTRL1, 0x08);
+ MDSS_PLL_REG_W(io->pll_base + 0x800, QSERDES_TX_L2_VMODE_CTRL1, 0x09);
+ MDSS_PLL_REG_W(io->pll_base + 0x400, QSERDES_TX_L0_VMODE_CTRL5, 0xA0);
+ MDSS_PLL_REG_W(io->pll_base + 0x400, QSERDES_TX_L0_VMODE_CTRL6, 0x01);
+ MDSS_PLL_REG_W(io->pll_base + 0x800, QSERDES_TX_L2_VMODE_CTRL5, 0xA0);
+ MDSS_PLL_REG_W(io->pll_base + 0x800, QSERDES_TX_L2_VMODE_CTRL6, 0x01);
+
+ MDSS_PLL_REG_W(io->pll_base + 0x400,
+ QSERDES_TX_L0_PARRATE_REC_DETECT_IDLE_EN, 0x40);
+ MDSS_PLL_REG_W(io->pll_base + 0x400,
+ QSERDES_TX_L0_TX_INTERFACE_MODE, 0x00);
+ MDSS_PLL_REG_W(io->pll_base + 0x600,
+ QSERDES_TX_L1_PARRATE_REC_DETECT_IDLE_EN, 0x40);
+ MDSS_PLL_REG_W(io->pll_base + 0x600,
+ QSERDES_TX_L1_TX_INTERFACE_MODE, 0x00);
+ MDSS_PLL_REG_W(io->pll_base + 0x800,
+ QSERDES_TX_L2_PARRATE_REC_DETECT_IDLE_EN, 0x40);
+ MDSS_PLL_REG_W(io->pll_base + 0x800,
+ QSERDES_TX_L2_TX_INTERFACE_MODE, 0x00);
+ MDSS_PLL_REG_W(io->pll_base + 0xA00,
+ QSERDES_TX_L3_PARRATE_REC_DETECT_IDLE_EN, 0x40);
+ MDSS_PLL_REG_W(io->pll_base + 0xA00,
+ QSERDES_TX_L3_TX_INTERFACE_MODE, 0x00);
+
+ return 0;
+}
+
+static int hdmi_20nm_vco_enable(struct clk *c)
+{
+ u32 ready_poll;
+ u32 time_out_loop;
+ /* Hardware recommended timeout iterator */
+ u32 time_out_max = 50000;
+
+ struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
+ struct mdss_pll_resources *io = vco->priv;
+
+ MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x00000000);
+ udelay(100);
+ /* memory barrier */
+ mb();
+ MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x00000003);
+ udelay(100);
+ /* memory barrier */
+ mb();
+ MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x00000009);
+ udelay(100);
+ /* memory barrier */
+ mb();
+
+ /* Poll for C_READY and PHY READY */
+ pr_debug("%s: Waiting for PHY Ready\n", __func__);
+ time_out_loop = 0;
+ do {
+ ready_poll = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_RESET_SM);
+ time_out_loop++;
+ udelay(10);
+ } while (((ready_poll & (1 << 6)) == 0) &&
+ (time_out_loop < time_out_max));
+ if (time_out_loop >= time_out_max)
+ pr_err("%s: ERROR: TIMED OUT BEFORE C READY\n", __func__);
+ else
+ pr_debug("%s: C READY\n", __func__);
+
+ /* Poll for PHY READY */
+ pr_debug("%s: Waiting for PHY Ready\n", __func__);
+ time_out_loop = 0;
+ do {
+ ready_poll = MDSS_PLL_REG_R(io->phy_base, HDMI_PHY_STATUS);
+ time_out_loop++;
+ udelay(1);
+ } while (((ready_poll & 0x1) == 0) && (time_out_loop < time_out_max));
+
+ if (time_out_loop >= time_out_max)
+ pr_err("%s: TIMED OUT BEFORE PHY READY\n", __func__);
+ else
+ pr_debug("%s: HDMI PHY READY\n", __func__);
+
+ io->pll_on = true;
+
+ return 0;
+}
+
+
+static int hdmi_20nm_vco_set_rate(struct clk *c, unsigned long rate)
+{
+ struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
+ struct mdss_pll_resources *io = vco->priv;
+ void __iomem *pll_base;
+ void __iomem *phy_base;
+ unsigned int set_power_dwn = 0;
+ int rc;
+
+ rc = mdss_pll_resource_enable(io, true);
+ if (rc) {
+ pr_err("pll resource can't be enabled\n");
+ return rc;
+ }
+
+ if (io->pll_on)
+ set_power_dwn = 1;
+
+ pll_base = io->pll_base;
+ phy_base = io->phy_base;
+
+ pr_debug("rate=%ld\n", rate);
+
+ hdmi_20nm_phy_pll_set_clk_rate(c, rate);
+
+ mdss_pll_resource_enable(io, false);
+
+ if (set_power_dwn)
+ hdmi_20nm_vco_enable(c);
+
+ vco->rate = rate;
+ vco->rate_set = true;
+
+ return 0;
+}
+
+static unsigned long hdmi_20nm_vco_get_rate(struct clk *c)
+{
+ unsigned long freq = 0;
+ int rc;
+ struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
+ struct mdss_pll_resources *io = vco->priv;
+
+ if (is_gdsc_disabled(io))
+ return 0;
+
+ rc = mdss_pll_resource_enable(io, true);
+ if (rc) {
+ pr_err("pll resource can't be enabled\n");
+ return rc;
+ }
+
+ mdss_pll_resource_enable(io, false);
+
+ return freq;
+}
+
+static long hdmi_20nm_vco_round_rate(struct clk *c, unsigned long rate)
+{
+ unsigned long rrate = rate;
+
+ pr_debug("rrate=%ld\n", rrate);
+
+ return rrate;
+}
+
+static int hdmi_20nm_vco_prepare(struct clk *c)
+{
+ struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
+ struct mdss_pll_resources *io = vco->priv;
+ int ret = 0;
+
+ pr_debug("rate=%ld\n", vco->rate);
+
+ if (!vco->rate_set && vco->rate)
+ ret = hdmi_20nm_vco_set_rate(c, vco->rate);
+
+ if (!ret) {
+ ret = mdss_pll_resource_enable(io, true);
+ if (ret)
+ pr_err("pll resource can't be enabled\n");
+ }
+
+ return ret;
+}
+
+static void hdmi_20nm_vco_unprepare(struct clk *c)
+{
+ struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
+ struct mdss_pll_resources *io = vco->priv;
+
+ vco->rate_set = false;
+
+ if (!io) {
+ pr_err("Invalid input parameter\n");
+ return;
+ }
+
+ if (!io->pll_on &&
+ mdss_pll_resource_enable(io, true)) {
+ pr_err("pll resource can't be enabled\n");
+ return;
+ }
+
+ io->handoff_resources = false;
+ mdss_pll_resource_enable(io, false);
+ io->pll_on = false;
+}
+
+static enum handoff hdmi_20nm_vco_handoff(struct clk *c)
+{
+ enum handoff ret = HANDOFF_DISABLED_CLK;
+ struct hdmi_pll_vco_clk *vco = to_hdmi_20nm_vco_clk(c);
+ struct mdss_pll_resources *io = vco->priv;
+
+ if (is_gdsc_disabled(io))
+ return HANDOFF_DISABLED_CLK;
+
+ if (mdss_pll_resource_enable(io, true)) {
+ pr_err("pll resource can't be enabled\n");
+ return ret;
+ }
+
+ io->handoff_resources = true;
+
+ if (hdmi_20nm_pll_lock_status(io)) {
+ io->pll_on = true;
+ c->rate = hdmi_20nm_vco_get_rate(c);
+ ret = HANDOFF_ENABLED_CLK;
+ } else {
+ io->handoff_resources = false;
+ mdss_pll_resource_enable(io, false);
+ }
+
+ pr_debug("done, ret=%d\n", ret);
+ return ret;
+}
+
+static const struct clk_ops hdmi_20nm_vco_clk_ops = {
+ .enable = hdmi_20nm_vco_enable,
+ .set_rate = hdmi_20nm_vco_set_rate,
+ .get_rate = hdmi_20nm_vco_get_rate,
+ .round_rate = hdmi_20nm_vco_round_rate,
+ .prepare = hdmi_20nm_vco_prepare,
+ .unprepare = hdmi_20nm_vco_unprepare,
+ .handoff = hdmi_20nm_vco_handoff,
+};
+
+static struct hdmi_pll_vco_clk hdmi_20nm_vco_clk = {
+ .ip_seti = (struct hdmi_pll_cfg[]){
+ {550890000, 0x03},
+ {589240000, 0x07},
+ {689290000, 0x03},
+ {727600000, 0x07},
+ {HDMI_PLL_TMDS_MAX, 0x03},
+ },
+ .cp_seti = (struct hdmi_pll_cfg[]){
+ {34440000, 0x3F},
+ {36830000, 0x2F},
+ {68870000, 0x3F},
+ {73660000, 0x2F},
+ {137730000, 0x3F},
+ {147310000, 0x2F},
+ {275450000, 0x3F},
+ {294620000, 0x2F},
+ {344650000, 0x3F},
+ {363800000, 0x2F},
+ {477960000, 0x3F},
+ {512530000, 0x2F},
+ {550890000, 0x1F},
+ {589240000, 0x2F},
+ {630900000, 0x3F},
+ {650590000, 0x2F},
+ {689290000, 0x1F},
+ {727600000, 0x2F},
+ {HDMI_PLL_TMDS_MAX, 0x3F},
+ },
+ .ip_setp = (struct hdmi_pll_cfg[]){
+ {497340000, 0x03},
+ {512530000, 0x07},
+ {535680000, 0x03},
+ {550890000, 0x07},
+ {574060000, 0x03},
+ {727600000, 0x07},
+ {HDMI_PLL_TMDS_MAX, 0x03},
+ },
+ .cp_setp = (struct hdmi_pll_cfg[]){
+ {36830000, 0x1F},
+ {40010000, 0x17},
+ {73660000, 0x1F},
+ {80000000, 0x17},
+ {147310000, 0x1F},
+ {160010000, 0x17},
+ {294620000, 0x1F},
+ {363800000, 0x17},
+ {497340000, 0x0F},
+ {512530000, 0x1F},
+ {535680000, 0x0F},
+ {550890000, 0x1F},
+ {574060000, 0x0F},
+ {589240000, 0x1F},
+ {727600000, 0x17},
+ {HDMI_PLL_TMDS_MAX, 0x07},
+ },
+ .crctrl = (struct hdmi_pll_cfg[]){
+ {40010000, 0xBB},
+ {40030000, 0x77},
+ {80000000, 0xBB},
+ {80060000, 0x77},
+ {160010000, 0xBB},
+ {160120000, 0x77},
+ {772930000, 0xBB},
+ {HDMI_PLL_TMDS_MAX, 0xFF},
+ },
+ .c = {
+ .dbg_name = "hdmi_20nm_vco_clk",
+ .ops = &hdmi_20nm_vco_clk_ops,
+ CLK_INIT(hdmi_20nm_vco_clk.c),
+ },
+};
+
+static struct clk_lookup hdmipllcc_8994[] = {
+ CLK_LIST(hdmi_20nm_vco_clk),
+};
+
+int hdmi_20nm_pll_clock_register(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ int rc = -ENOTSUPP;
+
+ if (!pll_res || !pll_res->phy_base || !pll_res->pll_base) {
+ pr_err("Invalid input parameters\n");
+ return -EPROBE_DEFER;
+ }
+
+ /* Set client data for vco, mux and div clocks */
+ hdmi_20nm_vco_clk.priv = pll_res;
+
+ rc = of_msm_clock_register(pdev->dev.of_node, hdmipllcc_8994,
+ ARRAY_SIZE(hdmipllcc_8994));
+ if (rc) {
+ pr_err("Clock register failed rc=%d\n", rc);
+ rc = -EPROBE_DEFER;
+ } else {
+ pr_debug("%s: SUCCESS\n", __func__);
+ }
+
+ return rc;
+}
diff --git a/drivers/clk/qcom/mdss/mdss-hdmi-pll-28hpm.c b/drivers/clk/qcom/mdss/mdss-hdmi-pll-28hpm.c
new file mode 100644
index 0000000..94fd4e5
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-hdmi-pll-28hpm.c
@@ -0,0 +1,1104 @@
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <linux/clk/msm-clk-provider.h>
+#include <linux/clk/msm-clk.h>
+#include <linux/clk/msm-clock-generic.h>
+
+#include "mdss-pll.h"
+#include "mdss-hdmi-pll.h"
+
+/* hdmi phy registers */
+#define HDMI_PHY_ANA_CFG0 (0x0000)
+#define HDMI_PHY_ANA_CFG1 (0x0004)
+#define HDMI_PHY_ANA_CFG2 (0x0008)
+#define HDMI_PHY_ANA_CFG3 (0x000C)
+#define HDMI_PHY_PD_CTRL0 (0x0010)
+#define HDMI_PHY_PD_CTRL1 (0x0014)
+#define HDMI_PHY_GLB_CFG (0x0018)
+#define HDMI_PHY_DCC_CFG0 (0x001C)
+#define HDMI_PHY_DCC_CFG1 (0x0020)
+#define HDMI_PHY_TXCAL_CFG0 (0x0024)
+#define HDMI_PHY_TXCAL_CFG1 (0x0028)
+#define HDMI_PHY_TXCAL_CFG2 (0x002C)
+#define HDMI_PHY_TXCAL_CFG3 (0x0030)
+#define HDMI_PHY_BIST_CFG0 (0x0034)
+#define HDMI_PHY_BIST_CFG1 (0x0038)
+#define HDMI_PHY_BIST_PATN0 (0x003C)
+#define HDMI_PHY_BIST_PATN1 (0x0040)
+#define HDMI_PHY_BIST_PATN2 (0x0044)
+#define HDMI_PHY_BIST_PATN3 (0x0048)
+#define HDMI_PHY_STATUS (0x005C)
+
+/* hdmi phy unified pll registers */
+#define HDMI_UNI_PLL_REFCLK_CFG (0x0000)
+#define HDMI_UNI_PLL_POSTDIV1_CFG (0x0004)
+#define HDMI_UNI_PLL_CHFPUMP_CFG (0x0008)
+#define HDMI_UNI_PLL_VCOLPF_CFG (0x000C)
+#define HDMI_UNI_PLL_VREG_CFG (0x0010)
+#define HDMI_UNI_PLL_PWRGEN_CFG (0x0014)
+#define HDMI_UNI_PLL_GLB_CFG (0x0020)
+#define HDMI_UNI_PLL_POSTDIV2_CFG (0x0024)
+#define HDMI_UNI_PLL_POSTDIV3_CFG (0x0028)
+#define HDMI_UNI_PLL_LPFR_CFG (0x002C)
+#define HDMI_UNI_PLL_LPFC1_CFG (0x0030)
+#define HDMI_UNI_PLL_LPFC2_CFG (0x0034)
+#define HDMI_UNI_PLL_SDM_CFG0 (0x0038)
+#define HDMI_UNI_PLL_SDM_CFG1 (0x003C)
+#define HDMI_UNI_PLL_SDM_CFG2 (0x0040)
+#define HDMI_UNI_PLL_SDM_CFG3 (0x0044)
+#define HDMI_UNI_PLL_SDM_CFG4 (0x0048)
+#define HDMI_UNI_PLL_SSC_CFG0 (0x004C)
+#define HDMI_UNI_PLL_SSC_CFG1 (0x0050)
+#define HDMI_UNI_PLL_SSC_CFG2 (0x0054)
+#define HDMI_UNI_PLL_SSC_CFG3 (0x0058)
+#define HDMI_UNI_PLL_LKDET_CFG0 (0x005C)
+#define HDMI_UNI_PLL_LKDET_CFG1 (0x0060)
+#define HDMI_UNI_PLL_LKDET_CFG2 (0x0064)
+#define HDMI_UNI_PLL_CAL_CFG0 (0x006C)
+#define HDMI_UNI_PLL_CAL_CFG1 (0x0070)
+#define HDMI_UNI_PLL_CAL_CFG2 (0x0074)
+#define HDMI_UNI_PLL_CAL_CFG3 (0x0078)
+#define HDMI_UNI_PLL_CAL_CFG4 (0x007C)
+#define HDMI_UNI_PLL_CAL_CFG5 (0x0080)
+#define HDMI_UNI_PLL_CAL_CFG6 (0x0084)
+#define HDMI_UNI_PLL_CAL_CFG7 (0x0088)
+#define HDMI_UNI_PLL_CAL_CFG8 (0x008C)
+#define HDMI_UNI_PLL_CAL_CFG9 (0x0090)
+#define HDMI_UNI_PLL_CAL_CFG10 (0x0094)
+#define HDMI_UNI_PLL_CAL_CFG11 (0x0098)
+#define HDMI_UNI_PLL_STATUS (0x00C0)
+
+#define HDMI_PLL_POLL_MAX_READS 10
+#define HDMI_PLL_POLL_TIMEOUT_US 50
+
+static inline struct hdmi_pll_vco_clk *to_hdmi_vco_clk(struct clk *clk)
+{
+ return container_of(clk, struct hdmi_pll_vco_clk, c);
+}
+
+static void hdmi_vco_disable(struct clk *c)
+{
+ struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
+ struct mdss_pll_resources *hdmi_pll_res = vco->priv;
+
+ if (!hdmi_pll_res) {
+ pr_err("Invalid input parameter\n");
+ return;
+ }
+
+ if (!hdmi_pll_res->pll_on &&
+ mdss_pll_resource_enable(hdmi_pll_res, true)) {
+ pr_err("pll resource can't be enabled\n");
+ return;
+ }
+
+ MDSS_PLL_REG_W(hdmi_pll_res->pll_base, HDMI_UNI_PLL_GLB_CFG, 0x0);
+ udelay(5);
+ MDSS_PLL_REG_W(hdmi_pll_res->phy_base, HDMI_PHY_GLB_CFG, 0x0);
+
+ hdmi_pll_res->handoff_resources = false;
+ mdss_pll_resource_enable(hdmi_pll_res, false);
+ hdmi_pll_res->pll_on = false;
+} /* hdmi_vco_disable */
+
+static int hdmi_vco_enable(struct clk *c)
+{
+ u32 status;
+ u32 max_reads, timeout_us;
+ int rc;
+ struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
+ struct mdss_pll_resources *hdmi_pll_res = vco->priv;
+
+ rc = mdss_pll_resource_enable(hdmi_pll_res, true);
+ if (rc) {
+ pr_err("pll resource can't be enabled\n");
+ return rc;
+ }
+
+ /* Global Enable */
+ MDSS_PLL_REG_W(hdmi_pll_res->phy_base, HDMI_PHY_GLB_CFG, 0x81);
+ /* Power up power gen */
+ MDSS_PLL_REG_W(hdmi_pll_res->phy_base, HDMI_PHY_PD_CTRL0, 0x00);
+ udelay(350);
+
+ /* PLL Power-Up */
+ MDSS_PLL_REG_W(hdmi_pll_res->pll_base, HDMI_UNI_PLL_GLB_CFG, 0x01);
+ udelay(5);
+ /* Power up PLL LDO */
+ MDSS_PLL_REG_W(hdmi_pll_res->pll_base, HDMI_UNI_PLL_GLB_CFG, 0x03);
+ udelay(350);
+
+ /* PLL Power-Up */
+ MDSS_PLL_REG_W(hdmi_pll_res->pll_base, HDMI_UNI_PLL_GLB_CFG, 0x0F);
+ udelay(350);
+
+ /* poll for PLL ready status */
+ max_reads = 20;
+ timeout_us = 100;
+ if (readl_poll_timeout_atomic(
+ (hdmi_pll_res->pll_base + HDMI_UNI_PLL_STATUS),
+ status, ((status & BIT(0)) == 1), max_reads, timeout_us)) {
+ pr_err("hdmi phy pll status=%x failed to Lock\n", status);
+ hdmi_vco_disable(c);
+ mdss_pll_resource_enable(hdmi_pll_res, false);
+ return -EINVAL;
+ }
+ pr_debug("hdmi phy pll is locked\n");
+
+ udelay(350);
+ /* poll for PHY ready status */
+ max_reads = 20;
+ timeout_us = 100;
+ if (readl_poll_timeout_atomic(
+ (hdmi_pll_res->phy_base + HDMI_PHY_STATUS),
+ status, ((status & BIT(0)) == 1), max_reads, timeout_us)) {
+ pr_err("hdmi phy status=%x failed to Lock\n", status);
+ hdmi_vco_disable(c);
+ mdss_pll_resource_enable(hdmi_pll_res, false);
+ return -EINVAL;
+ }
+ hdmi_pll_res->pll_on = true;
+ pr_debug("hdmi phy is locked\n");
+
+ return 0;
+} /* hdmi_vco_enable */
+
+
+static void hdmi_phy_pll_calculator(u32 vco_freq,
+ struct mdss_pll_resources *hdmi_pll_res)
+{
+ u32 ref_clk = 19200000;
+ u32 sdm_mode = 1;
+ u32 ref_clk_multiplier = sdm_mode == 1 ? 2 : 1;
+ u32 int_ref_clk_freq = ref_clk * ref_clk_multiplier;
+ u32 fbclk_pre_div = 1;
+ u32 ssc_mode = 0;
+ u32 kvco = 270;
+ u32 vdd = 95;
+ u32 ten_power_six = 1000000;
+ u32 ssc_ds_ppm = ssc_mode ? 5000 : 0;
+ u32 sdm_res = 16;
+ u32 ssc_tri_step = 32;
+ u32 ssc_freq = 2;
+ u64 ssc_ds = vco_freq * ssc_ds_ppm;
+ u32 div_in_freq = vco_freq / fbclk_pre_div;
+ u64 dc_offset = (div_in_freq / int_ref_clk_freq - 1) *
+ ten_power_six * 10;
+ u32 ssc_kdiv = (int_ref_clk_freq / ssc_freq) -
+ ten_power_six;
+ u64 sdm_freq_seed;
+ u32 ssc_tri_inc;
+ u64 fb_div_n;
+ void __iomem *pll_base = hdmi_pll_res->pll_base;
+ u32 val;
+
+ pr_debug("vco_freq = %u\n", vco_freq);
+
+ do_div(ssc_ds, (u64)ten_power_six);
+
+ fb_div_n = (u64)div_in_freq * (u64)ten_power_six * 10;
+ do_div(fb_div_n, int_ref_clk_freq);
+
+ sdm_freq_seed = ((fb_div_n - dc_offset - ten_power_six * 10) *
+ (1 << sdm_res) * 10) + 5;
+ do_div(sdm_freq_seed, ((u64)ten_power_six * 100));
+
+ ssc_tri_inc = (u32)ssc_ds;
+ ssc_tri_inc = (ssc_tri_inc / int_ref_clk_freq) * (1 << 16) /
+ ssc_tri_step;
+
+ val = (ref_clk_multiplier == 2 ? 1 : 0) +
+ ((fbclk_pre_div == 2 ? 1 : 0) * 16);
+ pr_debug("HDMI_UNI_PLL_REFCLK_CFG = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_REFCLK_CFG, val);
+
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CHFPUMP_CFG, 0x02);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VCOLPF_CFG, 0x19);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VREG_CFG, 0x04);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_PWRGEN_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV2_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV3_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFR_CFG, 0x0E);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC1_CFG, 0x20);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC2_CFG, 0x0D);
+
+ do_div(dc_offset, (u64)ten_power_six * 10);
+ val = sdm_mode == 0 ? 64 + dc_offset : 0;
+ pr_debug("HDMI_UNI_PLL_SDM_CFG0 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG0, val);
+
+ val = 64 + dc_offset;
+ pr_debug("HDMI_UNI_PLL_SDM_CFG1 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG1, val);
+
+ val = sdm_freq_seed & 0xFF;
+ pr_debug("HDMI_UNI_PLL_SDM_CFG2 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG2, val);
+
+ val = (sdm_freq_seed >> 8) & 0xFF;
+ pr_debug("HDMI_UNI_PLL_SDM_CFG3 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG3, val);
+
+ val = (sdm_freq_seed >> 16) & 0xFF;
+ pr_debug("HDMI_UNI_PLL_SDM_CFG4 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG4, val);
+
+ val = (ssc_mode == 0 ? 128 : 0) + (ssc_kdiv / ten_power_six);
+ pr_debug("HDMI_UNI_PLL_SSC_CFG0 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SSC_CFG0, val);
+
+ val = ssc_tri_inc & 0xFF;
+ pr_debug("HDMI_UNI_PLL_SSC_CFG1 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SSC_CFG1, val);
+
+ val = (ssc_tri_inc >> 8) & 0xFF;
+ pr_debug("HDMI_UNI_PLL_SSC_CFG2 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SSC_CFG2, val);
+
+ pr_debug("HDMI_UNI_PLL_SSC_CFG3 = 0x%x\n", ssc_tri_step);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SSC_CFG3, ssc_tri_step);
+
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG0, 0x10);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG1, 0x1A);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG2, 0x05);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG0, 0x0A);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG1, 0x04);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG2, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG3, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG4, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG5, 0x00);
+
+ val = (kvco * vdd * 10000) / 6;
+ val += 500000;
+ val /= ten_power_six;
+ pr_debug("HDMI_UNI_PLL_CAL_CFG6 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG6, val & 0xFF);
+
+ val = (kvco * vdd * 10000) / 6;
+ val -= ten_power_six;
+ val /= ten_power_six;
+ val = (val >> 8) & 0xFF;
+ pr_debug("HDMI_UNI_PLL_CAL_CFG7 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG7, val);
+
+ val = (ref_clk * 5) / ten_power_six;
+ pr_debug("HDMI_UNI_PLL_CAL_CFG8 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG8, val);
+
+ val = ((ref_clk * 5) / ten_power_six) >> 8;
+ pr_debug("HDMI_UNI_PLL_CAL_CFG9 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG9, val);
+
+ vco_freq /= ten_power_six;
+ val = vco_freq & 0xFF;
+ pr_debug("HDMI_UNI_PLL_CAL_CFG10 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG10, val);
+
+ val = vco_freq >> 8;
+ pr_debug("HDMI_UNI_PLL_CAL_CFG11 = 0x%x\n", val);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG11, val);
+} /* hdmi_phy_pll_calculator */
+
+static int hdmi_vco_set_rate(struct clk *c, unsigned long rate)
+{
+ struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
+ struct mdss_pll_resources *hdmi_pll_res = vco->priv;
+ void __iomem *pll_base;
+ void __iomem *phy_base;
+ unsigned int set_power_dwn = 0;
+ int rc;
+
+ rc = mdss_pll_resource_enable(hdmi_pll_res, true);
+ if (rc) {
+ pr_err("pll resource can't be enabled\n");
+ return rc;
+ }
+
+ if (hdmi_pll_res->pll_on) {
+ hdmi_vco_disable(c);
+ set_power_dwn = 1;
+ }
+
+ pll_base = hdmi_pll_res->pll_base;
+ phy_base = hdmi_pll_res->phy_base;
+
+ pr_debug("rate=%ld\n", rate);
+
+ switch (rate) {
+ case 0:
+ break;
+
+ case 756000000:
+ /* 640x480p60 */
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_GLB_CFG, 0x81);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_REFCLK_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VCOLPF_CFG, 0x19);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFR_CFG, 0x0E);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC1_CFG, 0x20);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC2_CFG, 0x0D);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG0, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG1, 0x52);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG2, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG3, 0xB0);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG4, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG0, 0x10);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG1, 0x1A);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG2, 0x05);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV2_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV3_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG2, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG8, 0x60);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG9, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG10, 0xF4);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG11, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL0, 0x1F);
+ udelay(50);
+
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x0F);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x10);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG0, 0xDB);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG1, 0x43);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG3, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VREG_CFG, 0x04);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG0, 0xD0);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG1, 0x1A);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG0, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG2, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG3, 0x05);
+ udelay(200);
+ break;
+
+ case 810000000:
+ /* 576p50/576i50 case */
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_GLB_CFG, 0x81);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_REFCLK_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VCOLPF_CFG, 0x19);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFR_CFG, 0x0E);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC1_CFG, 0x20);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC2_CFG, 0x0D);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG0, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG1, 0x54);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG2, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG3, 0x18);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG4, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG0, 0x10);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG1, 0x1A);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG2, 0x05);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV2_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV3_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG2, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG8, 0x60);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG9, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG10, 0x2A);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG11, 0x03);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL0, 0x1F);
+ udelay(50);
+
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x0F);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x10);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG0, 0xDB);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG1, 0x43);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG3, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VREG_CFG, 0x04);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG0, 0xD0);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG1, 0x1A);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG0, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG2, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG3, 0x05);
+ udelay(200);
+ break;
+
+ case 810900000:
+ /* 480p60/480i60 case */
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_GLB_CFG, 0x81);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_REFCLK_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VCOLPF_CFG, 0x19);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFR_CFG, 0x0E);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC1_CFG, 0x20);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC2_CFG, 0x0D);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG0, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG1, 0x54);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG2, 0x66);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG3, 0x1D);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG4, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG0, 0x10);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG1, 0x1A);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG2, 0x05);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV2_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV3_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG2, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG8, 0x60);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG9, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG10, 0x2A);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG11, 0x03);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL0, 0x1F);
+ udelay(50);
+
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x0F);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x10);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG0, 0xDB);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG1, 0x43);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG3, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VREG_CFG, 0x04);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG0, 0xD0);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG1, 0x1A);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG0, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG2, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG3, 0x05);
+ udelay(200);
+ break;
+
+ case 650000000:
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_GLB_CFG, 0x81);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_REFCLK_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VCOLPF_CFG, 0x19);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFR_CFG, 0x0E);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC1_CFG, 0x20);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC2_CFG, 0x0D);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG0, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG1, 0x4F);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG2, 0x55);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG3, 0xED);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG4, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG0, 0x10);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG1, 0x1A);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG2, 0x05);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV2_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV3_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG2, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG8, 0x60);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG9, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG10, 0x8A);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG11, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL0, 0x1F);
+ udelay(50);
+
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x0F);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x10);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG0, 0xDB);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG1, 0x43);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG3, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VREG_CFG, 0x04);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG0, 0xD0);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG1, 0x1A);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG0, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG2, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG3, 0x05);
+ udelay(200);
+ break;
+
+ case 742500000:
+ /*
+ * 720p60/720p50/1080i60/1080i50
+ * 1080p24/1080p30/1080p25 case
+ */
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_GLB_CFG, 0x81);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_REFCLK_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VCOLPF_CFG, 0x19);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFR_CFG, 0x0E);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC1_CFG, 0x20);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC2_CFG, 0x0D);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG0, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG1, 0x52);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG2, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG3, 0x56);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG4, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG0, 0x10);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG1, 0x1A);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG2, 0x05);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV2_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV3_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG2, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG8, 0x60);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG9, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG10, 0xE6);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG11, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL0, 0x1F);
+ udelay(50);
+
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x0F);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x10);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG0, 0xDB);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG1, 0x43);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG3, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VREG_CFG, 0x04);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG0, 0xD0);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG1, 0x1A);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG0, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG2, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG3, 0x05);
+ udelay(200);
+ break;
+
+ case 1080000000:
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_GLB_CFG, 0x81);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_REFCLK_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VCOLPF_CFG, 0x19);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFR_CFG, 0x0E);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC1_CFG, 0x20);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC2_CFG, 0x0D);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG0, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG1, 0x5B);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG2, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG3, 0x20);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG4, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG0, 0x10);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG1, 0x1A);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG2, 0x05);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV2_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV3_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG2, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG8, 0x60);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG9, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG10, 0x38);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG11, 0x04);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL0, 0x1F);
+ udelay(50);
+
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x0F);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x10);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG0, 0xDB);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG1, 0x43);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG3, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VREG_CFG, 0x04);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG0, 0xD0);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG1, 0x1A);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG0, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG2, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG3, 0x05);
+ udelay(200);
+ break;
+
+ case 1342500000:
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_GLB_CFG, 0x81);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_REFCLK_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VCOLPF_CFG, 0x19);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFR_CFG, 0x0E);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC1_CFG, 0x20);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC2_CFG, 0x0D);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG0, 0x36);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG1, 0x61);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG2, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG3, 0xF6);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG4, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG0, 0x10);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG1, 0x1A);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG2, 0x05);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV2_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV3_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG2, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG8, 0x60);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG9, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG10, 0x3E);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG11, 0x05);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL0, 0x1F);
+ udelay(50);
+
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x0F);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x10);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG0, 0xDB);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG1, 0x43);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x05);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG3, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VREG_CFG, 0x04);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG0, 0xD0);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG1, 0x1A);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG0, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG2, 0x11);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG3, 0x05);
+ udelay(200);
+ break;
+
+ case 1485000000:
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_GLB_CFG, 0x81);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_REFCLK_CFG, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VCOLPF_CFG, 0x19);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFR_CFG, 0x0E);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC1_CFG, 0x20);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LPFC2_CFG, 0x0D);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG0, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG1, 0x65);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG2, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG3, 0xAC);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_SDM_CFG4, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG0, 0x10);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG1, 0x1A);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_LKDET_CFG2, 0x05);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV2_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_POSTDIV3_CFG, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG2, 0x01);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG8, 0x60);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG9, 0x00);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG10, 0xCD);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_CAL_CFG11, 0x05);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL0, 0x1F);
+ udelay(50);
+
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x0F);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x10);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG0, 0xDB);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG1, 0x43);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x06);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG3, 0x03);
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VREG_CFG, 0x04);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG0, 0xD0);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG1, 0x1A);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG0, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG2, 0x02);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG3, 0x05);
+ udelay(200);
+ break;
+
+ default:
+ pr_debug("Use pll settings calculator for rate=%ld\n", rate);
+
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_GLB_CFG, 0x81);
+ hdmi_phy_pll_calculator(rate, hdmi_pll_res);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL0, 0x1F);
+ udelay(50);
+
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_GLB_CFG, 0x0F);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_PD_CTRL1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x10);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG0, 0xDB);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG1, 0x43);
+
+ if (rate < 825000000) {
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x01);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG3, 0x00);
+ } else if (rate >= 825000000 && rate < 1342500000) {
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x05);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG3, 0x03);
+ } else {
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG2, 0x06);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_ANA_CFG3, 0x03);
+ }
+
+ MDSS_PLL_REG_W(pll_base, HDMI_UNI_PLL_VREG_CFG, 0x04);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG0, 0xD0);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_DCC_CFG1, 0x1A);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG0, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG1, 0x00);
+
+ if (rate < 825000000)
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG2, 0x01);
+ else
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG2, 0x00);
+
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_TXCAL_CFG3, 0x05);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_BIST_PATN0, 0x62);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_BIST_PATN1, 0x03);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_BIST_PATN2, 0x69);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_BIST_PATN3, 0x02);
+
+ udelay(200);
+
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_BIST_CFG1, 0x00);
+ MDSS_PLL_REG_W(phy_base, HDMI_PHY_BIST_CFG0, 0x00);
+ }
+
+ /* Make sure writes complete before disabling iface clock */
+ mb();
+
+ mdss_pll_resource_enable(hdmi_pll_res, false);
+
+ if (set_power_dwn)
+ hdmi_vco_enable(c);
+
+ vco->rate = rate;
+ vco->rate_set = true;
+
+ return 0;
+} /* hdmi_pll_set_rate */
+
+/* HDMI PLL DIV CLK */
+
+static unsigned long hdmi_vco_get_rate(struct clk *c)
+{
+ unsigned long freq = 0;
+ int rc;
+ struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
+ struct mdss_pll_resources *hdmi_pll_res = vco->priv;
+
+ if (is_gdsc_disabled(hdmi_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(hdmi_pll_res, true);
+ if (rc) {
+ pr_err("pll resource can't be enabled\n");
+ return rc;
+ }
+
+ freq = MDSS_PLL_REG_R(hdmi_pll_res->pll_base,
+ HDMI_UNI_PLL_CAL_CFG11) << 8 |
+ MDSS_PLL_REG_R(hdmi_pll_res->pll_base, HDMI_UNI_PLL_CAL_CFG10);
+
+ switch (freq) {
+ case 742:
+ freq = 742500000;
+ break;
+ case 810:
+ if (MDSS_PLL_REG_R(hdmi_pll_res->pll_base,
+ HDMI_UNI_PLL_SDM_CFG3) == 0x18)
+ freq = 810000000;
+ else
+ freq = 810900000;
+ break;
+ case 1342:
+ freq = 1342500000;
+ break;
+ default:
+ freq *= 1000000;
+ }
+ mdss_pll_resource_enable(hdmi_pll_res, false);
+
+ return freq;
+}
+
+static long hdmi_vco_round_rate(struct clk *c, unsigned long rate)
+{
+ unsigned long rrate = rate;
+ struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
+
+ if (rate < vco->min_rate)
+ rrate = vco->min_rate;
+ if (rate > vco->max_rate)
+ rrate = vco->max_rate;
+
+ pr_debug("rrate=%ld\n", rrate);
+
+ return rrate;
+}
+
+static int hdmi_vco_prepare(struct clk *c)
+{
+ struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
+ int ret = 0;
+
+ pr_debug("rate=%ld\n", vco->rate);
+
+ if (!vco->rate_set && vco->rate)
+ ret = hdmi_vco_set_rate(c, vco->rate);
+
+ return ret;
+}
+
+static void hdmi_vco_unprepare(struct clk *c)
+{
+ struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
+
+ vco->rate_set = false;
+}
+
+static int hdmi_pll_lock_status(struct mdss_pll_resources *hdmi_pll_res)
+{
+ u32 status;
+ int pll_locked = 0;
+ int rc;
+
+ rc = mdss_pll_resource_enable(hdmi_pll_res, true);
+ if (rc) {
+ pr_err("pll resource can't be enabled\n");
+ return rc;
+ }
+
+ /* poll for PLL ready status */
+ if (readl_poll_timeout_atomic(
+ (hdmi_pll_res->phy_base + HDMI_PHY_STATUS),
+ status, ((status & BIT(0)) == 1),
+ HDMI_PLL_POLL_MAX_READS,
+ HDMI_PLL_POLL_TIMEOUT_US)) {
+ pr_debug("HDMI PLL status=%x failed to Lock\n", status);
+ pll_locked = 0;
+ } else {
+ pll_locked = 1;
+ }
+ mdss_pll_resource_enable(hdmi_pll_res, false);
+
+ return pll_locked;
+}
+
+static enum handoff hdmi_vco_handoff(struct clk *c)
+{
+ enum handoff ret = HANDOFF_DISABLED_CLK;
+ struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c);
+ struct mdss_pll_resources *hdmi_pll_res = vco->priv;
+
+ if (is_gdsc_disabled(hdmi_pll_res))
+ return HANDOFF_DISABLED_CLK;
+
+ if (mdss_pll_resource_enable(hdmi_pll_res, true)) {
+ pr_err("pll resource can't be enabled\n");
+ return ret;
+ }
+
+ hdmi_pll_res->handoff_resources = true;
+
+ if (hdmi_pll_lock_status(hdmi_pll_res)) {
+ hdmi_pll_res->pll_on = true;
+ c->rate = hdmi_vco_get_rate(c);
+ ret = HANDOFF_ENABLED_CLK;
+ } else {
+ hdmi_pll_res->handoff_resources = false;
+ mdss_pll_resource_enable(hdmi_pll_res, false);
+ }
+
+ pr_debug("done, ret=%d\n", ret);
+ return ret;
+}
+
+static const struct clk_ops hdmi_vco_clk_ops = {
+ .enable = hdmi_vco_enable,
+ .set_rate = hdmi_vco_set_rate,
+ .get_rate = hdmi_vco_get_rate,
+ .round_rate = hdmi_vco_round_rate,
+ .prepare = hdmi_vco_prepare,
+ .unprepare = hdmi_vco_unprepare,
+ .disable = hdmi_vco_disable,
+ .handoff = hdmi_vco_handoff,
+};
+
+static struct hdmi_pll_vco_clk hdmi_vco_clk = {
+ .min_rate = 600000000,
+ .max_rate = 1800000000,
+ .c = {
+ .dbg_name = "hdmi_vco_clk",
+ .ops = &hdmi_vco_clk_ops,
+ CLK_INIT(hdmi_vco_clk.c),
+ },
+};
+
+struct div_clk hdmipll_div1_clk = {
+ .data = {
+ .div = 1,
+ .min_div = 1,
+ .max_div = 1,
+ },
+ .c = {
+ .parent = &hdmi_vco_clk.c,
+ .dbg_name = "hdmipll_div1_clk",
+ .ops = &clk_ops_div,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(hdmipll_div1_clk.c),
+ },
+};
+
+struct div_clk hdmipll_div2_clk = {
+ .data = {
+ .div = 2,
+ .min_div = 2,
+ .max_div = 2,
+ },
+ .c = {
+ .parent = &hdmi_vco_clk.c,
+ .dbg_name = "hdmipll_div2_clk",
+ .ops = &clk_ops_div,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(hdmipll_div2_clk.c),
+ },
+};
+
+struct div_clk hdmipll_div4_clk = {
+ .data = {
+ .div = 4,
+ .min_div = 4,
+ .max_div = 4,
+ },
+ .c = {
+ .parent = &hdmi_vco_clk.c,
+ .dbg_name = "hdmipll_div4_clk",
+ .ops = &clk_ops_div,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(hdmipll_div4_clk.c),
+ },
+};
+
+struct div_clk hdmipll_div6_clk = {
+ .data = {
+ .div = 6,
+ .min_div = 6,
+ .max_div = 6,
+ },
+ .c = {
+ .parent = &hdmi_vco_clk.c,
+ .dbg_name = "hdmipll_div6_clk",
+ .ops = &clk_ops_div,
+ .flags = CLKFLAG_NO_RATE_CACHE,
+ CLK_INIT(hdmipll_div6_clk.c),
+ },
+};
+
+static int hdmipll_set_mux_sel(struct mux_clk *clk, int mux_sel)
+{
+ struct mdss_pll_resources *hdmi_pll_res = clk->priv;
+ int rc;
+
+ rc = mdss_pll_resource_enable(hdmi_pll_res, true);
+ if (rc) {
+ pr_err("pll resource can't be enabled\n");
+ return rc;
+ }
+
+ pr_debug("mux_sel=%d\n", mux_sel);
+ MDSS_PLL_REG_W(hdmi_pll_res->pll_base,
+ HDMI_UNI_PLL_POSTDIV1_CFG, mux_sel);
+ mdss_pll_resource_enable(hdmi_pll_res, false);
+
+ return 0;
+}
+
+static int hdmipll_get_mux_sel(struct mux_clk *clk)
+{
+ int rc;
+ int mux_sel = 0;
+ struct mdss_pll_resources *hdmi_pll_res = clk->priv;
+
+ if (is_gdsc_disabled(hdmi_pll_res))
+ return 0;
+
+ rc = mdss_pll_resource_enable(hdmi_pll_res, true);
+ if (rc) {
+ pr_err("pll resource can't be enabled\n");
+ return rc;
+ }
+
+ mux_sel = MDSS_PLL_REG_R(hdmi_pll_res->pll_base,
+ HDMI_UNI_PLL_POSTDIV1_CFG);
+ mdss_pll_resource_enable(hdmi_pll_res, false);
+ mux_sel &= 0x03;
+ pr_debug("mux_sel=%d\n", mux_sel);
+
+ return mux_sel;
+}
+
+static struct clk_mux_ops hdmipll_mux_ops = {
+ .set_mux_sel = hdmipll_set_mux_sel,
+ .get_mux_sel = hdmipll_get_mux_sel,
+};
+
+static const struct clk_ops hdmi_mux_ops;
+
+static int hdmi_mux_prepare(struct clk *c)
+{
+ int ret = 0;
+
+ if (c && c->ops && c->ops->set_rate)
+ ret = c->ops->set_rate(c, c->rate);
+
+ return ret;
+}
+
+struct mux_clk hdmipll_mux_clk = {
+ MUX_SRC_LIST(
+ { &hdmipll_div1_clk.c, 0 },
+ { &hdmipll_div2_clk.c, 1 },
+ { &hdmipll_div4_clk.c, 2 },
+ { &hdmipll_div6_clk.c, 3 },
+ ),
+ .ops = &hdmipll_mux_ops,
+ .c = {
+ .parent = &hdmipll_div1_clk.c,
+ .dbg_name = "hdmipll_mux_clk",
+ .ops = &hdmi_mux_ops,
+ CLK_INIT(hdmipll_mux_clk.c),
+ },
+};
+
+struct div_clk hdmipll_clk_src = {
+ .data = {
+ .div = 5,
+ .min_div = 5,
+ .max_div = 5,
+ },
+ .c = {
+ .parent = &hdmipll_mux_clk.c,
+ .dbg_name = "hdmipll_clk_src",
+ .ops = &clk_ops_div,
+ CLK_INIT(hdmipll_clk_src.c),
+ },
+};
+
+static struct clk_lookup hdmipllcc_8974[] = {
+ CLK_LOOKUP("extp_clk_src", hdmipll_clk_src.c,
+ "fd8c0000.qcom,mmsscc-mdss"),
+};
+
+int hdmi_pll_clock_register(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ int rc = -ENOTSUPP;
+
+ if (!pll_res || !pll_res->phy_base || !pll_res->pll_base) {
+ pr_err("Invalid input parameters\n");
+ return -EPROBE_DEFER;
+ }
+
+ /* Set client data for vco, mux and div clocks */
+ hdmipll_clk_src.priv = pll_res;
+ hdmipll_mux_clk.priv = pll_res;
+ hdmipll_div1_clk.priv = pll_res;
+ hdmipll_div2_clk.priv = pll_res;
+ hdmipll_div4_clk.priv = pll_res;
+ hdmipll_div6_clk.priv = pll_res;
+ hdmi_vco_clk.priv = pll_res;
+
+ /* Set hdmi mux clock operation */
+ hdmi_mux_ops = clk_ops_gen_mux;
+ hdmi_mux_ops.prepare = hdmi_mux_prepare;
+
+ rc = of_msm_clock_register(pdev->dev.of_node, hdmipllcc_8974,
+ ARRAY_SIZE(hdmipllcc_8974));
+ if (rc) {
+ pr_err("Clock register failed rc=%d\n", rc);
+ rc = -EPROBE_DEFER;
+ }
+
+ return rc;
+}
diff --git a/drivers/clk/qcom/mdss/mdss-hdmi-pll.h b/drivers/clk/qcom/mdss/mdss-hdmi-pll.h
new file mode 100644
index 0000000..612b7c4
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-hdmi-pll.h
@@ -0,0 +1,41 @@
+/* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MDSS_HDMI_PLL_H
+#define __MDSS_HDMI_PLL_H
+
+struct hdmi_pll_cfg {
+ unsigned long vco_rate;
+ u32 reg;
+};
+
+struct hdmi_pll_vco_clk {
+ unsigned long rate; /* current vco rate */
+ unsigned long min_rate; /* min vco rate */
+ unsigned long max_rate; /* max vco rate */
+ bool rate_set;
+ struct hdmi_pll_cfg *ip_seti;
+ struct hdmi_pll_cfg *cp_seti;
+ struct hdmi_pll_cfg *ip_setp;
+ struct hdmi_pll_cfg *cp_setp;
+ struct hdmi_pll_cfg *crctrl;
+ void *priv;
+
+ struct clk c;
+};
+
+int hdmi_pll_clock_register(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res);
+
+int hdmi_20nm_pll_clock_register(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res);
+#endif
diff --git a/drivers/clk/qcom/mdss/mdss-pll-util.c b/drivers/clk/qcom/mdss/mdss-pll-util.c
new file mode 100644
index 0000000..4d9cade9
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-pll-util.c
@@ -0,0 +1,352 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk/msm-clock-generic.h>
+
+#include "mdss-pll.h"
+
+int mdss_pll_util_resource_init(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ int rc = 0;
+ struct dss_module_power *mp = &pll_res->mp;
+
+ rc = msm_dss_config_vreg(&pdev->dev,
+ mp->vreg_config, mp->num_vreg, 1);
+ if (rc) {
+ pr_err("Vreg config failed rc=%d\n", rc);
+ goto vreg_err;
+ }
+
+ rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk);
+ if (rc) {
+ pr_err("Clock get failed rc=%d\n", rc);
+ goto clk_err;
+ }
+
+ return rc;
+
+clk_err:
+ msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
+vreg_err:
+ return rc;
+}
+
+/**
+ * mdss_pll_get_mp_by_reg_name() -- Find power module by regulator name
+ *@pll_res: Pointer to the PLL resource
+ *@name: Regulator name as specified in the pll dtsi
+ *
+ * This is a helper function to retrieve the regulator information
+ * for each pll resource.
+ */
+struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res
+ , char *name)
+{
+
+ struct dss_vreg *regulator = NULL;
+ int i;
+
+ if ((pll_res == NULL) || (pll_res->mp.vreg_config == NULL)) {
+ pr_err("%s Invalid PLL resource\n", __func__);
+ goto error;
+ }
+
+ regulator = pll_res->mp.vreg_config;
+
+ for (i = 0; i < pll_res->mp.num_vreg; i++) {
+ if (!strcmp(name, regulator->vreg_name)) {
+ pr_debug("Found regulator match for %s\n", name);
+ break;
+ }
+ regulator++;
+ }
+
+error:
+ return regulator;
+}
+
+void mdss_pll_util_resource_deinit(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ struct dss_module_power *mp = &pll_res->mp;
+
+ msm_dss_put_clk(mp->clk_config, mp->num_clk);
+
+ msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0);
+}
+
+void mdss_pll_util_resource_release(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ struct dss_module_power *mp = &pll_res->mp;
+
+ devm_kfree(&pdev->dev, mp->clk_config);
+ devm_kfree(&pdev->dev, mp->vreg_config);
+ mp->num_vreg = 0;
+ mp->num_clk = 0;
+}
+
+int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res,
+ bool enable)
+{
+ int rc = 0;
+ struct dss_module_power *mp = &pll_res->mp;
+
+ if (enable) {
+ rc = msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable);
+ if (rc) {
+ pr_err("Failed to enable vregs rc=%d\n", rc);
+ goto vreg_err;
+ }
+
+ rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
+ if (rc) {
+ pr_err("Failed to set clock rate rc=%d\n", rc);
+ goto clk_err;
+ }
+
+ rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
+ if (rc) {
+ pr_err("clock enable failed rc:%d\n", rc);
+ goto clk_err;
+ }
+ } else {
+ msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
+
+ msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable);
+ }
+
+ return rc;
+
+clk_err:
+ msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, 0);
+vreg_err:
+ return rc;
+}
+
+static int mdss_pll_util_parse_dt_supply(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ int i = 0, rc = 0;
+ u32 tmp = 0;
+ struct device_node *of_node = NULL, *supply_root_node = NULL;
+ struct device_node *supply_node = NULL;
+ struct dss_module_power *mp = &pll_res->mp;
+
+ of_node = pdev->dev.of_node;
+
+ mp->num_vreg = 0;
+ supply_root_node = of_get_child_by_name(of_node,
+ "qcom,platform-supply-entries");
+ if (!supply_root_node) {
+ pr_err("no supply entry present\n");
+ return rc;
+ }
+
+ for_each_child_of_node(supply_root_node, supply_node) {
+ mp->num_vreg++;
+ }
+
+ if (mp->num_vreg == 0) {
+ pr_debug("no vreg\n");
+ return rc;
+ }
+ pr_debug("vreg found. count=%d\n", mp->num_vreg);
+
+ mp->vreg_config = devm_kzalloc(&pdev->dev, sizeof(struct dss_vreg) *
+ mp->num_vreg, GFP_KERNEL);
+ if (!mp->vreg_config) {
+ rc = -ENOMEM;
+ return rc;
+ }
+
+ for_each_child_of_node(supply_root_node, supply_node) {
+
+ const char *st = NULL;
+
+ rc = of_property_read_string(supply_node,
+ "qcom,supply-name", &st);
+ if (rc) {
+ pr_err(":error reading name. rc=%d\n", rc);
+ goto error;
+ }
+
+ strlcpy(mp->vreg_config[i].vreg_name, st,
+ sizeof(mp->vreg_config[i].vreg_name));
+
+ rc = of_property_read_u32(supply_node,
+ "qcom,supply-min-voltage", &tmp);
+ if (rc) {
+ pr_err(": error reading min volt. rc=%d\n", rc);
+ goto error;
+ }
+ mp->vreg_config[i].min_voltage = tmp;
+
+ rc = of_property_read_u32(supply_node,
+ "qcom,supply-max-voltage", &tmp);
+ if (rc) {
+ pr_err(": error reading max volt. rc=%d\n", rc);
+ goto error;
+ }
+ mp->vreg_config[i].max_voltage = tmp;
+
+ rc = of_property_read_u32(supply_node,
+ "qcom,supply-enable-load", &tmp);
+ if (rc) {
+ pr_err(": error reading enable load. rc=%d\n", rc);
+ goto error;
+ }
+ mp->vreg_config[i].enable_load = tmp;
+
+ rc = of_property_read_u32(supply_node,
+ "qcom,supply-disable-load", &tmp);
+ if (rc) {
+ pr_err(": error reading disable load. rc=%d\n", rc);
+ goto error;
+ }
+ mp->vreg_config[i].disable_load = tmp;
+
+ rc = of_property_read_u32(supply_node,
+ "qcom,supply-pre-on-sleep", &tmp);
+ if (rc)
+ pr_debug("error reading supply pre sleep value. rc=%d\n",
+ rc);
+
+ mp->vreg_config[i].pre_on_sleep = (!rc ? tmp : 0);
+
+ rc = of_property_read_u32(supply_node,
+ "qcom,supply-pre-off-sleep", &tmp);
+ if (rc)
+ pr_debug("error reading supply pre sleep value. rc=%d\n",
+ rc);
+
+ mp->vreg_config[i].pre_off_sleep = (!rc ? tmp : 0);
+
+ rc = of_property_read_u32(supply_node,
+ "qcom,supply-post-on-sleep", &tmp);
+ if (rc)
+ pr_debug("error reading supply post sleep value. rc=%d\n",
+ rc);
+
+ mp->vreg_config[i].post_on_sleep = (!rc ? tmp : 0);
+
+ rc = of_property_read_u32(supply_node,
+ "qcom,supply-post-off-sleep", &tmp);
+ if (rc)
+ pr_debug("error reading supply post sleep value. rc=%d\n",
+ rc);
+
+ mp->vreg_config[i].post_off_sleep = (!rc ? tmp : 0);
+
+ pr_debug("%s min=%d, max=%d, enable=%d, disable=%d, preonsleep=%d, postonsleep=%d, preoffsleep=%d, postoffsleep=%d\n",
+ mp->vreg_config[i].vreg_name,
+ mp->vreg_config[i].min_voltage,
+ mp->vreg_config[i].max_voltage,
+ mp->vreg_config[i].enable_load,
+ mp->vreg_config[i].disable_load,
+ mp->vreg_config[i].pre_on_sleep,
+ mp->vreg_config[i].post_on_sleep,
+ mp->vreg_config[i].pre_off_sleep,
+ mp->vreg_config[i].post_off_sleep);
+ ++i;
+
+ rc = 0;
+ }
+
+ return rc;
+
+error:
+ if (mp->vreg_config) {
+ devm_kfree(&pdev->dev, mp->vreg_config);
+ mp->vreg_config = NULL;
+ mp->num_vreg = 0;
+ }
+
+ return rc;
+}
+
+static int mdss_pll_util_parse_dt_clock(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ u32 i = 0, rc = 0;
+ struct dss_module_power *mp = &pll_res->mp;
+ const char *clock_name;
+ u32 clock_rate;
+
+ mp->num_clk = of_property_count_strings(pdev->dev.of_node,
+ "clock-names");
+ if (mp->num_clk <= 0) {
+ pr_err("clocks are not defined\n");
+ goto clk_err;
+ }
+
+ mp->clk_config = devm_kzalloc(&pdev->dev,
+ sizeof(struct dss_clk) * mp->num_clk, GFP_KERNEL);
+ if (!mp->clk_config) {
+ rc = -ENOMEM;
+ mp->num_clk = 0;
+ goto clk_err;
+ }
+
+ for (i = 0; i < mp->num_clk; i++) {
+ of_property_read_string_index(pdev->dev.of_node, "clock-names",
+ i, &clock_name);
+ strlcpy(mp->clk_config[i].clk_name, clock_name,
+ sizeof(mp->clk_config[i].clk_name));
+
+ of_property_read_u32_index(pdev->dev.of_node, "clock-rate",
+ i, &clock_rate);
+ mp->clk_config[i].rate = clock_rate;
+
+ if (!clock_rate)
+ mp->clk_config[i].type = DSS_CLK_AHB;
+ else
+ mp->clk_config[i].type = DSS_CLK_PCLK;
+ }
+
+clk_err:
+ return rc;
+}
+
+int mdss_pll_util_resource_parse(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ int rc = 0;
+ struct dss_module_power *mp = &pll_res->mp;
+
+ rc = mdss_pll_util_parse_dt_supply(pdev, pll_res);
+ if (rc) {
+ pr_err("vreg parsing failed rc=%d\n", rc);
+ goto end;
+ }
+
+ rc = mdss_pll_util_parse_dt_clock(pdev, pll_res);
+ if (rc) {
+ pr_err("clock name parsing failed rc=%d", rc);
+ goto clk_err;
+ }
+
+ return rc;
+
+clk_err:
+ devm_kfree(&pdev->dev, mp->vreg_config);
+ mp->num_vreg = 0;
+end:
+ return rc;
+}
diff --git a/drivers/clk/qcom/mdss/mdss-pll.c b/drivers/clk/qcom/mdss/mdss-pll.c
new file mode 100644
index 0000000..cd27c41
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-pll.c
@@ -0,0 +1,436 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <linux/clk/msm-clock-generic.h>
+
+#include "mdss-pll.h"
+#include "mdss-edp-pll.h"
+#include "mdss-dsi-pll.h"
+#include "mdss-hdmi-pll.h"
+
+int mdss_pll_resource_enable(struct mdss_pll_resources *pll_res, bool enable)
+{
+ int rc = 0;
+ int changed = 0;
+
+ if (!pll_res) {
+ pr_err("Invalid input parameters\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Don't turn off resources during handoff or add more than
+ * 1 refcount.
+ */
+ if (pll_res->handoff_resources &&
+ (!enable || (enable & pll_res->resource_enable))) {
+ pr_debug("Do not turn on/off pll resources during handoff case\n");
+ return rc;
+ }
+
+ if (enable) {
+ if (pll_res->resource_ref_cnt == 0)
+ changed++;
+ pll_res->resource_ref_cnt++;
+ } else {
+ if (pll_res->resource_ref_cnt) {
+ pll_res->resource_ref_cnt--;
+ if (pll_res->resource_ref_cnt == 0)
+ changed++;
+ } else {
+ pr_err("PLL Resources already OFF\n");
+ }
+ }
+
+ if (changed) {
+ rc = mdss_pll_util_resource_enable(pll_res, enable);
+ if (rc)
+ pr_err("Resource update failed rc=%d\n", rc);
+ else
+ pll_res->resource_enable = enable;
+ }
+
+ return rc;
+}
+
+static int mdss_pll_resource_init(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ if (!pdev || !pll_res) {
+ pr_err("Invalid input parameters\n");
+ return -EINVAL;
+ }
+
+ return mdss_pll_util_resource_init(pdev, pll_res);
+}
+
+static void mdss_pll_resource_deinit(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ if (!pdev || !pll_res) {
+ pr_err("Invalid input parameters\n");
+ return;
+ }
+
+ mdss_pll_util_resource_deinit(pdev, pll_res);
+}
+
+static void mdss_pll_resource_release(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ if (!pdev || !pll_res) {
+ pr_err("Invalid input parameters\n");
+ return;
+ }
+
+ mdss_pll_util_resource_release(pdev, pll_res);
+}
+
+static int mdss_pll_resource_parse(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ int rc = 0;
+ const char *compatible_stream;
+
+ if (!pdev || !pll_res) {
+ pr_err("Invalid input parameters\n");
+ return -EINVAL;
+ }
+
+ rc = mdss_pll_util_resource_parse(pdev, pll_res);
+ if (rc) {
+ pr_err("Failed to parse the resources rc=%d\n", rc);
+ goto end;
+ }
+
+ compatible_stream = of_get_property(pdev->dev.of_node,
+ "compatible", NULL);
+ if (!compatible_stream) {
+ pr_err("Failed to parse the compatible stream\n");
+ goto err;
+ }
+
+ if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8916")) {
+ pll_res->pll_interface_type = MDSS_DSI_PLL_LPM;
+ pll_res->target_id = MDSS_PLL_TARGET_8916;
+ } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8939")) {
+ pll_res->pll_interface_type = MDSS_DSI_PLL_LPM;
+ pll_res->target_id = MDSS_PLL_TARGET_8939;
+ } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8909")) {
+ pll_res->pll_interface_type = MDSS_DSI_PLL_LPM;
+ pll_res->target_id = MDSS_PLL_TARGET_8909;
+ } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8974")) {
+ pll_res->pll_interface_type = MDSS_DSI_PLL_HPM;
+ pll_res->target_id = MDSS_PLL_TARGET_8974;
+ } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8994")) {
+ pll_res->pll_interface_type = MDSS_DSI_PLL_20NM;
+ pll_res->target_id = MDSS_PLL_TARGET_8994;
+ } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8992")) {
+ pll_res->pll_interface_type = MDSS_DSI_PLL_20NM;
+ pll_res->target_id = MDSS_PLL_TARGET_8992;
+ } else if (!strcmp(compatible_stream, "qcom,mdss_edp_pll")) {
+ pll_res->pll_interface_type = MDSS_EDP_PLL;
+ } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll")) {
+ pll_res->pll_interface_type = MDSS_HDMI_PLL;
+ } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8994")) {
+ pll_res->pll_interface_type = MDSS_HDMI_PLL_20NM;
+ } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8992")) {
+ pll_res->pll_interface_type = MDSS_HDMI_PLL_20NM;
+ } else {
+ goto err;
+ }
+
+ return rc;
+
+err:
+ mdss_pll_resource_release(pdev, pll_res);
+end:
+ return rc;
+}
+
+static int mdss_pll_clock_register(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res)
+{
+ int rc;
+
+ if (!pdev || !pll_res) {
+ pr_err("Invalid input parameters\n");
+ return -EINVAL;
+ }
+
+ switch (pll_res->pll_interface_type) {
+ case MDSS_DSI_PLL_LPM:
+ rc = dsi_pll_clock_register_lpm(pdev, pll_res);
+ break;
+ case MDSS_DSI_PLL_HPM:
+ rc = dsi_pll_clock_register_hpm(pdev, pll_res);
+ break;
+ case MDSS_DSI_PLL_20NM:
+ rc = dsi_pll_clock_register_20nm(pdev, pll_res);
+ break;
+ case MDSS_EDP_PLL:
+ rc = edp_pll_clock_register(pdev, pll_res);
+ break;
+ case MDSS_HDMI_PLL:
+ rc = hdmi_pll_clock_register(pdev, pll_res);
+ case MDSS_HDMI_PLL_20NM:
+ rc = hdmi_20nm_pll_clock_register(pdev, pll_res);
+ break;
+ case MDSS_UNKNOWN_PLL:
+ default:
+ rc = -EINVAL;
+ break;
+ }
+
+ if (rc)
+ pr_err("Pll parent clock register failed rc=%d\n", rc);
+
+ return rc;
+}
+
+static int mdss_pll_probe(struct platform_device *pdev)
+{
+ int rc = 0;
+ const char *label;
+ struct resource *pll_base_reg;
+ struct resource *phy_base_reg;
+ struct resource *dynamic_pll_base_reg;
+ struct resource *gdsc_base_reg;
+ struct mdss_pll_resources *pll_res;
+
+ if (!pdev->dev.of_node) {
+ pr_err("MDSS pll driver only supports device tree probe\n");
+ rc = -ENOTSUPP;
+ goto error;
+ }
+
+ label = of_get_property(pdev->dev.of_node, "label", NULL);
+ if (!label)
+ pr_info("%d: MDSS pll label not specified\n", __LINE__);
+ else
+ pr_info("MDSS pll label = %s\n", label);
+
+ pll_res = devm_kzalloc(&pdev->dev, sizeof(struct mdss_pll_resources),
+ GFP_KERNEL);
+ if (!pll_res) {
+ rc = -ENOMEM;
+ goto error;
+ }
+ platform_set_drvdata(pdev, pll_res);
+
+ rc = of_property_read_u32(pdev->dev.of_node, "cell-index",
+ &pll_res->index);
+ if (rc) {
+ pr_err("Unable to get the cell-index rc=%d\n", rc);
+ pll_res->index = 0;
+ }
+
+ pll_base_reg = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM, "pll_base");
+ if (!pll_base_reg) {
+ pr_err("Unable to get the pll base resources\n");
+ rc = -ENOMEM;
+ goto io_error;
+ }
+
+ pll_res->pll_base = ioremap(pll_base_reg->start,
+ resource_size(pll_base_reg));
+ if (!pll_res->pll_base) {
+ pr_err("Unable to remap pll base resources\n");
+ rc = -ENOMEM;
+ goto io_error;
+ }
+
+ rc = mdss_pll_resource_parse(pdev, pll_res);
+ if (rc) {
+ pr_err("Pll resource parsing from dt failed rc=%d\n", rc);
+ goto res_parse_error;
+ }
+
+ /*
+ * DSI PLL 1 is leaking current whenever MDSS GDSC is toggled. Need to
+ * map PLL1 registers along with the PLl0 so that we can manually turn
+ * off PLL1.
+ */
+ if (pll_res->pll_interface_type == MDSS_DSI_PLL_20NM) {
+ struct resource *pll_1_base_reg;
+
+ pll_1_base_reg = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM, "pll_1_base");
+ if (pll_1_base_reg) {
+ pll_res->pll_1_base = ioremap(pll_1_base_reg->start,
+ resource_size(pll_1_base_reg));
+ if (!pll_res->pll_1_base)
+ pr_err("Unable to remap pll 1 base resources\n");
+ } else {
+ pr_err("Unable to get the pll 1 base resource\n");
+ }
+ }
+
+ phy_base_reg = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM, "phy_base");
+ if (!phy_base_reg) {
+ /* This resource is mandatory for HDMI pll */
+ if (pll_res->pll_interface_type == MDSS_HDMI_PLL) {
+ pr_err("Unable to get the phy base resources\n");
+ rc = -ENOMEM;
+ goto phy_io_error;
+ }
+ } else {
+ pll_res->phy_base = ioremap(phy_base_reg->start,
+ resource_size(phy_base_reg));
+ if (!pll_res->phy_base) {
+ pr_err("Unable to remap pll phy base resources\n");
+ rc = -ENOMEM;
+ goto phy_io_error;
+ }
+ }
+
+ dynamic_pll_base_reg = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM, "dynamic_pll_base");
+ if (dynamic_pll_base_reg) {
+ pll_res->dyn_pll_base = ioremap(dynamic_pll_base_reg->start,
+ resource_size(dynamic_pll_base_reg));
+ if (!pll_res->dyn_pll_base) {
+ pr_err("Unable to remap dynamic pll base resources\n");
+ rc = -ENOMEM;
+ goto dyn_pll_io_error;
+ }
+ }
+
+ gdsc_base_reg = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM, "gdsc_base");
+ if (!gdsc_base_reg) {
+ pr_err("Unable to get the gdsc base resource\n");
+ rc = -ENOMEM;
+ goto gdsc_io_error;
+ }
+ pll_res->gdsc_base = ioremap(gdsc_base_reg->start,
+ resource_size(gdsc_base_reg));
+ if (!pll_res->gdsc_base) {
+ pr_err("Unable to remap gdsc base resources\n");
+ rc = -ENOMEM;
+ goto gdsc_io_error;
+ }
+
+ rc = mdss_pll_resource_init(pdev, pll_res);
+ if (rc) {
+ pr_err("Pll resource init failed rc=%d\n", rc);
+ goto res_init_error;
+ }
+
+ rc = mdss_pll_clock_register(pdev, pll_res);
+ if (rc) {
+ pr_err("Pll clock register failed rc=%d\n", rc);
+ goto clock_register_error;
+ }
+
+ return rc;
+
+clock_register_error:
+ mdss_pll_resource_deinit(pdev, pll_res);
+res_init_error:
+ if (pll_res->gdsc_base)
+ iounmap(pll_res->gdsc_base);
+gdsc_io_error:
+ if (pll_res->dyn_pll_base)
+ iounmap(pll_res->dyn_pll_base);
+dyn_pll_io_error:
+ if (pll_res->phy_base)
+ iounmap(pll_res->phy_base);
+phy_io_error:
+ if (pll_res->pll_1_base)
+ iounmap(pll_res->pll_1_base);
+ mdss_pll_resource_release(pdev, pll_res);
+res_parse_error:
+ iounmap(pll_res->pll_base);
+io_error:
+ devm_kfree(&pdev->dev, pll_res);
+error:
+ return rc;
+}
+
+static int mdss_pll_remove(struct platform_device *pdev)
+{
+ struct mdss_pll_resources *pll_res;
+
+ pll_res = platform_get_drvdata(pdev);
+ if (!pll_res) {
+ pr_err("Invalid PLL resource data");
+ return 0;
+ }
+
+ mdss_pll_resource_deinit(pdev, pll_res);
+ if (pll_res->phy_base)
+ iounmap(pll_res->phy_base);
+ if (pll_res->gdsc_base)
+ iounmap(pll_res->gdsc_base);
+ mdss_pll_resource_release(pdev, pll_res);
+ iounmap(pll_res->pll_base);
+ devm_kfree(&pdev->dev, pll_res);
+ return 0;
+}
+
+static const struct of_device_id mdss_pll_dt_match[] = {
+ {.compatible = "qcom,mdss_dsi_pll_8974"},
+ {.compatible = "qcom,mdss_dsi_pll_8994"},
+ {.compatible = "qcom,mdss_hdmi_pll_8994"},
+ {.compatible = "qcom,mdss_dsi_pll_8992"},
+ {.compatible = "qcom,mdss_hdmi_pll_8992"},
+ {.compatible = "qcom,mdss_dsi_pll_8916"},
+ {.compatible = "qcom,mdss_dsi_pll_8939"},
+ {.compatible = "qcom,mdss_dsi_pll_8909"},
+ {.compatible = "qcom,mdss_edp_pll"},
+ {.compatible = "qcom,mdss_hdmi_pll"},
+ {}
+};
+
+MODULE_DEVICE_TABLE(of, mdss_clock_dt_match);
+
+static struct platform_driver mdss_pll_driver = {
+ .probe = mdss_pll_probe,
+ .remove = mdss_pll_remove,
+ .driver = {
+ .name = "mdss_pll",
+ .of_match_table = mdss_pll_dt_match,
+ },
+};
+
+static int __init mdss_pll_driver_init(void)
+{
+ int rc;
+
+ rc = platform_driver_register(&mdss_pll_driver);
+ if (rc)
+ pr_err("mdss_register_pll_driver() failed!\n");
+
+ return rc;
+}
+subsys_initcall(mdss_pll_driver_init);
+
+static void __exit mdss_pll_driver_deinit(void)
+{
+ platform_driver_unregister(&mdss_pll_driver);
+}
+module_exit(mdss_pll_driver_deinit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("mdss pll driver");
diff --git a/drivers/clk/qcom/mdss/mdss-pll.h b/drivers/clk/qcom/mdss/mdss-pll.h
new file mode 100644
index 0000000..057d173
--- /dev/null
+++ b/drivers/clk/qcom/mdss/mdss-pll.h
@@ -0,0 +1,171 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MDSS_PLL_H
+#define __MDSS_PLL_H
+
+#include <linux/mdss_io_util.h>
+#include <linux/io.h>
+
+#define MDSS_PLL_REG_W(base, offset, data) \
+ writel_relaxed((data), (base) + (offset))
+#define MDSS_PLL_REG_R(base, offset) readl_relaxed((base) + (offset))
+
+#define PLL_CALC_DATA(addr0, addr1, data0, data1) \
+ (((data1) << 24) | (((addr1)/4) << 16) | ((data0) << 8) | ((addr0)/4))
+
+#define MDSS_DYN_PLL_REG_W(base, offset, addr0, addr1, data0, data1) \
+ writel_relaxed(PLL_CALC_DATA(addr0, addr1, data0, data1), \
+ (base) + (offset))
+
+enum {
+ MDSS_DSI_PLL_LPM,
+ MDSS_DSI_PLL_HPM,
+ MDSS_DSI_PLL_20NM,
+ MDSS_EDP_PLL,
+ MDSS_HDMI_PLL,
+ MDSS_HDMI_PLL_20NM,
+ MDSS_UNKNOWN_PLL,
+};
+
+enum {
+ MDSS_PLL_TARGET_8974,
+ MDSS_PLL_TARGET_8994,
+ MDSS_PLL_TARGET_8992,
+ MDSS_PLL_TARGET_8916,
+ MDSS_PLL_TARGET_8939,
+ MDSS_PLL_TARGET_8909,
+};
+
+struct mdss_pll_resources {
+
+ /* Pll specific resources like GPIO, power supply, clocks, etc*/
+ struct dss_module_power mp;
+
+ /*
+ * dsi/edp/hmdi plls' base register, phy, gdsc and dynamic refresh
+ * register mapping
+ */
+ void __iomem *pll_base;
+ void __iomem *pll_1_base;
+ void __iomem *phy_base;
+ void __iomem *gdsc_base;
+ void __iomem *dyn_pll_base;
+
+ s64 vco_current_rate;
+ s64 vco_ref_clk_rate;
+
+ /*
+ * Certain pll's needs to update the same vco rate after resume in
+ * suspend/resume scenario. Cached the vco rate for such plls.
+ */
+ unsigned long vco_cached_rate;
+
+ /* dsi/edp/hmdi pll interface type */
+ u32 pll_interface_type;
+
+ /*
+ * Target ID. Used in pll_register API for valid target check before
+ * registering the PLL clocks.
+ */
+ u32 target_id;
+
+ /* HW recommended delay during configuration of vco clock rate */
+ u32 vco_delay;
+
+ /* Ref-count of the PLL resources */
+ u32 resource_ref_cnt;
+
+ /*
+ * Keep track to resource status to avoid updating same status for the
+ * pll from different paths
+ */
+ bool resource_enable;
+
+ /*
+ * Certain plls' do not allow vco rate update if it is on. Keep track of
+ * status for them to turn on/off after set rate success.
+ */
+ bool pll_on;
+
+ /*
+ * handoff_status is true of pll is already enabled by bootloader with
+ * continuous splash enable case. Clock API will call the handoff API
+ * to enable the status. It is disabled if continuous splash
+ * feature is disabled.
+ */
+ bool handoff_resources;
+
+ /*
+ * caching the pll trim codes in the case of dynamic refresh
+ */
+ int cache_pll_trim_codes[2];
+
+ /*
+ * for maintaining the status of saving trim codes
+ */
+ bool reg_upd;
+
+ /*
+ * Notifier callback for MDSS gdsc regulator events
+ */
+ struct notifier_block gdsc_cb;
+
+ /*
+ * Worker function to call PLL off event
+ */
+ struct work_struct pll_off;
+
+ /*
+ * PLL index if multiple index are available. Eg. in case of
+ * DSI we have 2 plls.
+ */
+ uint32_t index;
+
+};
+
+struct mdss_pll_vco_calc {
+ s32 div_frac_start1;
+ s32 div_frac_start2;
+ s32 div_frac_start3;
+ s64 dec_start1;
+ s64 dec_start2;
+ s64 pll_plllock_cmp1;
+ s64 pll_plllock_cmp2;
+ s64 pll_plllock_cmp3;
+};
+
+static inline bool is_gdsc_disabled(struct mdss_pll_resources *pll_res)
+{
+ if (!pll_res->gdsc_base) {
+ WARN(1, "gdsc_base register is not defined\n");
+ return true;
+ }
+
+ return ((readl_relaxed(pll_res->gdsc_base + 0x4) & BIT(31)) &&
+ (!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? false : true;
+}
+
+int mdss_pll_resource_enable(struct mdss_pll_resources *pll_res, bool enable);
+int mdss_pll_util_resource_init(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res);
+void mdss_pll_util_resource_deinit(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res);
+void mdss_pll_util_resource_release(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res);
+int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res,
+ bool enable);
+int mdss_pll_util_resource_parse(struct platform_device *pdev,
+ struct mdss_pll_resources *pll_res);
+struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res
+ , char *name);
+#endif
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 7290eef..f4ce22d 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -54,6 +54,16 @@
If unsure, say no.
+config REGULATOR_PROXY_CONSUMER
+ bool "Boot time regulator proxy consumer support"
+ help
+ This driver provides support for boot time regulator proxy requests.
+ It can enforce a specified voltage range, set a minimum current,
+ and/or keep a regulator enabled. It is needed in circumstances where
+ reducing one or more of these three quantities will cause hardware to
+ stop working if performed before the driver managing the hardware has
+ probed.
+
config REGULATOR_88PM800
tristate "Marvell 88PM800 Power regulators"
depends on MFD_88PM800
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index faafafa..2e466b1 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_REGULATOR_FIXED_VOLTAGE) += fixed.o
obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER) += virtual.o
obj-$(CONFIG_REGULATOR_USERSPACE_CONSUMER) += userspace-consumer.o
+obj-$(CONFIG_REGULATOR_PROXY_CONSUMER) += proxy-consumer.o
obj-$(CONFIG_REGULATOR_88PM800) += 88pm800.o
obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 8994db2..183fa22 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -4443,6 +4443,8 @@
dev_set_drvdata(&rdev->dev, rdev);
rdev_init_debugfs(rdev);
+ rdev->proxy_consumer = regulator_proxy_consumer_register(dev,
+ config->of_node);
/* try to resolve regulators supply since a new one was registered */
class_for_each_device(®ulator_class, NULL, NULL,
@@ -4482,6 +4484,7 @@
regulator_disable(rdev->supply);
regulator_put(rdev->supply);
}
+ regulator_proxy_consumer_unregister(rdev->proxy_consumer);
rdev_deinit_debugfs(rdev);
mutex_lock(®ulator_list_mutex);
flush_work(&rdev->disable_work.work);
diff --git a/drivers/regulator/proxy-consumer.c b/drivers/regulator/proxy-consumer.c
new file mode 100644
index 0000000..99b1959
--- /dev/null
+++ b/drivers/regulator/proxy-consumer.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2013-2014, 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/proxy-consumer.h>
+
+struct proxy_consumer {
+ struct list_head list;
+ struct regulator *reg;
+ bool enable;
+ int min_uV;
+ int max_uV;
+ u32 current_uA;
+};
+
+static DEFINE_MUTEX(proxy_consumer_list_mutex);
+static LIST_HEAD(proxy_consumer_list);
+static bool proxy_consumers_removed;
+
+/**
+ * regulator_proxy_consumer_register() - conditionally register a proxy consumer
+ * for the specified regulator and set its boot time parameters
+ * @reg_dev: Device pointer of the regulator
+ * @reg_node: Device node pointer of the regulator
+ *
+ * Returns a struct proxy_consumer pointer corresponding to the regulator on
+ * success, ERR_PTR() if an error occurred, or NULL if no proxy consumer is
+ * needed for the regulator. This function calls
+ * regulator_get(reg_dev, "proxy") after first checking if any proxy consumer
+ * properties are present in the reg_node device node. After that, the voltage,
+ * minimum current, and/or the enable state will be set based upon the device
+ * node property values.
+ */
+struct proxy_consumer *regulator_proxy_consumer_register(struct device *reg_dev,
+ struct device_node *reg_node)
+{
+ struct proxy_consumer *consumer = NULL;
+ const char *reg_name = "";
+ u32 voltage[2] = {0};
+ int rc;
+
+ /* Return immediately if no proxy consumer properties are specified. */
+ if (!of_find_property(reg_node, "qcom,proxy-consumer-enable", NULL)
+ && !of_find_property(reg_node, "qcom,proxy-consumer-voltage", NULL)
+ && !of_find_property(reg_node, "qcom,proxy-consumer-current", NULL))
+ return NULL;
+
+ mutex_lock(&proxy_consumer_list_mutex);
+
+ /* Do not register new consumers if they cannot be removed later. */
+ if (proxy_consumers_removed) {
+ rc = -EPERM;
+ goto unlock;
+ }
+
+ if (dev_name(reg_dev))
+ reg_name = dev_name(reg_dev);
+
+ consumer = kzalloc(sizeof(*consumer), GFP_KERNEL);
+ if (!consumer) {
+ rc = -ENOMEM;
+ goto unlock;
+ }
+
+ consumer->enable
+ = of_property_read_bool(reg_node, "qcom,proxy-consumer-enable");
+ of_property_read_u32(reg_node, "qcom,proxy-consumer-current",
+ &consumer->current_uA);
+ rc = of_property_read_u32_array(reg_node, "qcom,proxy-consumer-voltage",
+ voltage, 2);
+ if (!rc) {
+ consumer->min_uV = voltage[0];
+ consumer->max_uV = voltage[1];
+ }
+
+ dev_dbg(reg_dev, "proxy consumer request: enable=%d, voltage_range=[%d, %d] uV, min_current=%d uA\n",
+ consumer->enable, consumer->min_uV, consumer->max_uV,
+ consumer->current_uA);
+
+ consumer->reg = regulator_get(reg_dev, "proxy");
+ if (IS_ERR_OR_NULL(consumer->reg)) {
+ rc = PTR_ERR(consumer->reg);
+ pr_err("regulator_get() failed for %s, rc=%d\n", reg_name, rc);
+ goto unlock;
+ }
+
+ if (consumer->max_uV > 0 && consumer->min_uV <= consumer->max_uV) {
+ rc = regulator_set_voltage(consumer->reg, consumer->min_uV,
+ consumer->max_uV);
+ if (rc) {
+ pr_err("regulator_set_voltage %s failed, rc=%d\n",
+ reg_name, rc);
+ goto free_regulator;
+ }
+ }
+
+ if (consumer->current_uA > 0) {
+ rc = regulator_set_load(consumer->reg,
+ consumer->current_uA);
+ if (rc < 0) {
+ pr_err("regulator_set_load %s failed, rc=%d\n",
+ reg_name, rc);
+ goto remove_voltage;
+ }
+ }
+
+ if (consumer->enable) {
+ rc = regulator_enable(consumer->reg);
+ if (rc) {
+ pr_err("regulator_enable %s failed, rc=%d\n", reg_name,
+ rc);
+ goto remove_current;
+ }
+ }
+
+ list_add(&consumer->list, &proxy_consumer_list);
+ mutex_unlock(&proxy_consumer_list_mutex);
+
+ return consumer;
+
+remove_current:
+ regulator_set_load(consumer->reg, 0);
+remove_voltage:
+ regulator_set_voltage(consumer->reg, 0, INT_MAX);
+free_regulator:
+ regulator_put(consumer->reg);
+unlock:
+ kfree(consumer);
+ mutex_unlock(&proxy_consumer_list_mutex);
+ return ERR_PTR(rc);
+}
+
+/* proxy_consumer_list_mutex must be held by caller. */
+static int regulator_proxy_consumer_remove(struct proxy_consumer *consumer)
+{
+ int rc = 0;
+
+ if (consumer->enable) {
+ rc = regulator_disable(consumer->reg);
+ if (rc)
+ pr_err("regulator_disable failed, rc=%d\n", rc);
+ }
+
+ if (consumer->current_uA > 0) {
+ rc = regulator_set_load(consumer->reg, 0);
+ if (rc < 0)
+ pr_err("regulator_set_load failed, rc=%d\n",
+ rc);
+ }
+
+ if (consumer->max_uV > 0 && consumer->min_uV <= consumer->max_uV) {
+ rc = regulator_set_voltage(consumer->reg, 0, INT_MAX);
+ if (rc)
+ pr_err("regulator_set_voltage failed, rc=%d\n", rc);
+ }
+
+ regulator_put(consumer->reg);
+ list_del(&consumer->list);
+ kfree(consumer);
+
+ return rc;
+}
+
+/**
+ * regulator_proxy_consumer_unregister() - unregister a proxy consumer and
+ * remove its boot time requests
+ * @consumer: Pointer to proxy_consumer to be removed
+ *
+ * Returns 0 on success or errno on failure. This function removes all requests
+ * made by the proxy consumer in regulator_proxy_consumer_register() and then
+ * frees the consumer's resources.
+ */
+int regulator_proxy_consumer_unregister(struct proxy_consumer *consumer)
+{
+ int rc = 0;
+
+ if (IS_ERR_OR_NULL(consumer))
+ return 0;
+
+ mutex_lock(&proxy_consumer_list_mutex);
+ if (!proxy_consumers_removed)
+ rc = regulator_proxy_consumer_remove(consumer);
+ mutex_unlock(&proxy_consumer_list_mutex);
+
+ return rc;
+}
+
+/*
+ * Remove all proxy requests at late_initcall_sync. The assumption is that all
+ * devices have probed at this point and made their own regulator requests.
+ */
+static int __init regulator_proxy_consumer_remove_all(void)
+{
+ struct proxy_consumer *consumer;
+ struct proxy_consumer *temp;
+
+ mutex_lock(&proxy_consumer_list_mutex);
+ proxy_consumers_removed = true;
+
+ if (!list_empty(&proxy_consumer_list))
+ pr_info("removing regulator proxy consumer requests\n");
+
+ list_for_each_entry_safe(consumer, temp, &proxy_consumer_list, list) {
+ regulator_proxy_consumer_remove(consumer);
+ }
+ mutex_unlock(&proxy_consumer_list_mutex);
+
+ return 0;
+}
+late_initcall_sync(regulator_proxy_consumer_remove_all);
diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h
index e59f776..ee79113 100644
--- a/include/linux/regulator/driver.h
+++ b/include/linux/regulator/driver.h
@@ -18,6 +18,7 @@
#include <linux/device.h>
#include <linux/notifier.h>
#include <linux/regulator/consumer.h>
+#include <linux/regulator/proxy-consumer.h>
struct regmap;
struct regulator_dev;
@@ -433,6 +434,7 @@
/* time when this regulator was disabled last time */
unsigned long last_off_jiffy;
+ struct proxy_consumer *proxy_consumer;
struct regulator *debug_consumer;
};
diff --git a/include/linux/regulator/proxy-consumer.h b/include/linux/regulator/proxy-consumer.h
new file mode 100644
index 0000000..10ba541
--- /dev/null
+++ b/include/linux/regulator/proxy-consumer.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _LINUX_REGULATOR_PROXY_CONSUMER_H_
+#define _LINUX_REGULATOR_PROXY_CONSUMER_H_
+
+#include <linux/device.h>
+#include <linux/of.h>
+
+struct proxy_consumer;
+
+#ifdef CONFIG_REGULATOR_PROXY_CONSUMER
+
+struct proxy_consumer *regulator_proxy_consumer_register(struct device *reg_dev,
+ struct device_node *reg_node);
+
+int regulator_proxy_consumer_unregister(struct proxy_consumer *consumer);
+
+#else
+
+static inline struct proxy_consumer *regulator_proxy_consumer_register(
+ struct device *reg_dev, struct device_node *reg_node)
+{ return NULL; }
+
+static inline int regulator_proxy_consumer_unregister(
+ struct proxy_consumer *consumer)
+{ return 0; }
+
+#endif
+
+#endif
diff --git a/include/sound/pcm.h b/include/sound/pcm.h
index af1fb37..df5b292 100644
--- a/include/sound/pcm.h
+++ b/include/sound/pcm.h
@@ -68,6 +68,8 @@
int (*close)(struct snd_pcm_substream *substream);
int (*ioctl)(struct snd_pcm_substream * substream,
unsigned int cmd, void *arg);
+ int (*compat_ioctl)(struct snd_pcm_substream *substream,
+ unsigned int cmd, void *arg);
int (*hw_params)(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params);
int (*hw_free)(struct snd_pcm_substream *substream);
@@ -482,6 +484,7 @@
#endif /* CONFIG_SND_VERBOSE_PROCFS */
/* misc flags */
unsigned int hw_opened: 1;
+ unsigned int hw_no_buffer: 1; /* substream may not have a buffer */
};
#define SUBSTREAM_BUSY(substream) ((substream)->ref_count > 0)
diff --git a/include/sound/soc.h b/include/sound/soc.h
index f8d3912..b5b820b 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -383,6 +383,10 @@
#define SND_SOC_COMP_ORDER_LATE 1
#define SND_SOC_COMP_ORDER_LAST 2
+/* DAI Link Host Mode Support */
+#define SND_SOC_DAI_LINK_NO_HOST 0x1
+#define SND_SOC_DAI_LINK_OPT_HOST 0x2
+
/*
* Bias levels
*
@@ -760,6 +764,7 @@
unsigned int channels_min; /* min channels */
unsigned int channels_max; /* max channels */
unsigned int sig_bits; /* number of bits of content */
+ const char *aif_name; /* DAPM AIF widget name */
};
/* SoC audio ops */
@@ -1057,6 +1062,12 @@
/* This DAI link can route to other DAI links at runtime (Frontend)*/
unsigned int dynamic:1;
+ /*
+ * This DAI can support no host IO (no pcm data is
+ * copied to from host)
+ */
+ unsigned int no_host_mode:2;
+
/* DPCM capture and Playback support */
unsigned int dpcm_capture:1;
unsigned int dpcm_playback:1;
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index e84ec63..45a2b23 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -9442,6 +9442,13 @@
raw_spin_unlock(&busiest_rq->lock);
+ if (push_task) {
+ if (push_task_detached)
+ attach_one_task(target_rq, push_task);
+ put_task_struct(push_task);
+ clear_reserved(target_cpu);
+ }
+
if (p)
attach_one_task(target_rq, p);
diff --git a/sound/core/pcm_compat.c b/sound/core/pcm_compat.c
index 1f64ab0..1867398 100644
--- a/sound/core/pcm_compat.c
+++ b/sound/core/pcm_compat.c
@@ -655,6 +655,25 @@
#endif /* CONFIG_X86_X32 */
};
+static int snd_compressed_ioctl32(struct snd_pcm_substream *substream,
+ unsigned int cmd, void __user *arg)
+{
+ struct snd_pcm_runtime *runtime;
+ int err = 0;
+
+ if (PCM_RUNTIME_CHECK(substream))
+ return -ENXIO;
+ runtime = substream->runtime;
+ if (substream->ops->compat_ioctl) {
+ err = substream->ops->compat_ioctl(substream, cmd, arg);
+ } else {
+ err = -ENOIOCTLCMD;
+ pr_err("%s failed cmd = %d\n", __func__, cmd);
+ }
+ pr_debug("%s called with cmd = %d\n", __func__, cmd);
+ return err;
+}
+
static long snd_pcm_ioctl_compat(struct file *file, unsigned int cmd, unsigned long arg)
{
struct snd_pcm_file *pcm_file;
@@ -734,6 +753,9 @@
case SNDRV_PCM_IOCTL_CHANNEL_INFO_X32:
return snd_pcm_ioctl_channel_info_x32(substream, argp);
#endif /* CONFIG_X86_X32 */
+ default:
+ if (_IOC_TYPE(cmd) == 'C')
+ return snd_compressed_ioctl32(substream, cmd, argp);
}
return -ENOIOCTLCMD;
diff --git a/sound/core/pcm_lib.c b/sound/core/pcm_lib.c
index bb12615..294230d 100644
--- a/sound/core/pcm_lib.c
+++ b/sound/core/pcm_lib.c
@@ -2115,6 +2115,9 @@
struct snd_pcm_runtime *runtime;
if (PCM_RUNTIME_CHECK(substream))
return -ENXIO;
+ /* TODO: consider and -EINVAL here */
+ if (substream->hw_no_buffer)
+ snd_printd("%s: warning this PCM is host less\n", __func__);
runtime = substream->runtime;
if (snd_BUG_ON(!substream->ops->copy && !runtime->dma_area))
return -EINVAL;
diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
index 9d33c1e..f04abc4 100644
--- a/sound/core/pcm_native.c
+++ b/sound/core/pcm_native.c
@@ -1034,6 +1034,7 @@
if (runtime->status->state != SNDRV_PCM_STATE_PREPARED)
return -EBADFD;
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
+ !substream->hw_no_buffer &&
!snd_pcm_playback_data(substream))
return -EPIPE;
runtime->trigger_tstamp_latched = false;
diff --git a/sound/soc/soc-compress.c b/sound/soc/soc-compress.c
index bf7b52f..bd3b40b 100644
--- a/sound/soc/soc-compress.c
+++ b/sound/soc/soc-compress.c
@@ -728,6 +728,14 @@
rtd->compr = compr;
compr->private_data = rtd;
+ if (platform->driver->pcm_new) {
+ ret = platform->driver->pcm_new(rtd);
+ if (ret < 0) {
+ pr_err("asoc: compress pcm constructor failed\n");
+ goto compr_err;
+ }
+ }
+
printk(KERN_INFO "compress asoc: %s <-> %s mapping ok\n", codec_dai->name,
cpu_dai->name);
return ret;
diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c
index ab07789..00bf9a7 100644
--- a/sound/soc/soc-pcm.c
+++ b/sound/soc/soc-pcm.c
@@ -25,6 +25,7 @@
#include <linux/workqueue.h>
#include <linux/export.h>
#include <linux/debugfs.h>
+#include <linux/dma-mapping.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
@@ -35,6 +36,30 @@
#define DPCM_MAX_BE_USERS 8
/*
+ * ASoC no host IO hardware.
+ * TODO: fine tune these values for all host less transfers.
+ */
+static const struct snd_pcm_hardware no_host_hardware = {
+ .info = SNDRV_PCM_INFO_MMAP |
+ SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_INTERLEAVED |
+ SNDRV_PCM_INFO_PAUSE |
+ SNDRV_PCM_INFO_RESUME,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S32_LE,
+ .period_bytes_min = PAGE_SIZE >> 2,
+ .period_bytes_max = PAGE_SIZE >> 1,
+ .periods_min = 2,
+ .periods_max = 4,
+ /*
+ * Increase the max buffer bytes as PAGE_SIZE bytes is
+ * not enough to encompass all the scenarios sent by
+ * userspapce.
+ */
+ .buffer_bytes_max = PAGE_SIZE * 4,
+};
+
+/*
* snd_soc_dai_stream_valid() - check if a DAI supports the given stream
*
* Returns true if the DAI supports the indicated stream type.
@@ -156,6 +181,8 @@
const struct snd_pcm_hardware *hw)
{
struct snd_pcm_runtime *runtime = substream->runtime;
+ if (!runtime)
+ return 0;
runtime->hw.info = hw->info;
runtime->hw.formats = hw->formats;
runtime->hw.period_bytes_min = hw->period_bytes_min;
@@ -469,6 +496,9 @@
mutex_lock_nested(&rtd->pcm_mutex, rtd->pcm_subclass);
+ if (rtd->dai_link->no_host_mode == SND_SOC_DAI_LINK_NO_HOST)
+ snd_soc_set_runtime_hwparams(substream, &no_host_hardware);
+
/* startup the audio subsystem */
if (cpu_dai->driver->ops && cpu_dai->driver->ops->startup) {
ret = cpu_dai->driver->ops->startup(substream, cpu_dai);
@@ -856,10 +886,31 @@
mutex_lock_nested(&rtd->pcm_mutex, rtd->pcm_subclass);
+ /* perform any hw_params fixups */
+ if ((rtd->dai_link->no_host_mode == SND_SOC_DAI_LINK_NO_HOST) &&
+ rtd->dai_link->be_hw_params_fixup) {
+ ret = rtd->dai_link->be_hw_params_fixup(rtd,
+ params);
+ if (ret < 0)
+ dev_err(rtd->card->dev, "ASoC: fixup failed for %s\n",
+ rtd->dai_link->name);
+ }
+
ret = soc_pcm_params_symmetry(substream, params);
if (ret)
goto out;
+ /* perform any hw_params fixups */
+ if ((rtd->dai_link->no_host_mode == SND_SOC_DAI_LINK_NO_HOST) &&
+ rtd->dai_link->be_hw_params_fixup) {
+ ret = rtd->dai_link->be_hw_params_fixup(rtd,
+ params);
+ if (ret < 0) {
+ dev_err(rtd->card->dev, "ASoC: fixup failed for %s\n",
+ rtd->dai_link->name);
+ }
+ }
+
if (rtd->dai_link->ops && rtd->dai_link->ops->hw_params) {
ret = rtd->dai_link->ops->hw_params(substream, params);
if (ret < 0) {
@@ -930,6 +981,23 @@
cpu_dai->sample_bits =
snd_pcm_format_physical_width(params_format(params));
+ /* malloc a page for hostless IO.
+ * FIXME: rework with alsa-lib changes so that this malloc is
+ * not required.
+ */
+ if (rtd->dai_link->no_host_mode == SND_SOC_DAI_LINK_NO_HOST) {
+ substream->dma_buffer.dev.type = SNDRV_DMA_TYPE_DEV;
+ substream->dma_buffer.dev.dev = rtd->dev;
+ substream->dma_buffer.dev.dev->coherent_dma_mask =
+ DMA_BIT_MASK(sizeof(dma_addr_t) * 8);
+ substream->dma_buffer.private_data = NULL;
+
+ arch_setup_dma_ops(substream->dma_buffer.dev.dev,
+ 0, 0, NULL, 0);
+ ret = snd_pcm_lib_malloc_pages(substream, PAGE_SIZE);
+ if (ret < 0)
+ goto platform_err;
+ }
out:
mutex_unlock(&rtd->pcm_mutex);
return ret;
@@ -1012,6 +1080,8 @@
if (cpu_dai->driver->ops && cpu_dai->driver->ops->hw_free)
cpu_dai->driver->ops->hw_free(substream, cpu_dai);
+ if (rtd->dai_link->no_host_mode == SND_SOC_DAI_LINK_NO_HOST)
+ snd_pcm_lib_free_pages(substream);
mutex_unlock(&rtd->pcm_mutex);
return 0;
}
@@ -2653,6 +2723,7 @@
struct snd_soc_dai *codec_dai;
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
struct snd_pcm *pcm;
+ struct snd_pcm_str *stream;
char new_name[64];
int ret = 0, playback = 0, capture = 0;
int i;
@@ -2725,6 +2796,22 @@
goto out;
}
+ /* setup any hostless PCMs - i.e. no host IO is performed */
+ if (rtd->dai_link->no_host_mode) {
+ if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
+ stream = &pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
+ stream->substream->hw_no_buffer = 1;
+ snd_soc_set_runtime_hwparams(stream->substream,
+ &no_host_hardware);
+ }
+ if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
+ stream = &pcm->streams[SNDRV_PCM_STREAM_CAPTURE];
+ stream->substream->hw_no_buffer = 1;
+ snd_soc_set_runtime_hwparams(stream->substream,
+ &no_host_hardware);
+ }
+ }
+
/* ASoC PCM operations */
if (rtd->dai_link->dynamic) {
rtd->ops.open = dpcm_fe_dai_open;