| commit | 22bd1f7ef40a1c0f2ba796ba7cd80013adcb835d | [log] [tgz] |
|---|---|---|
| author | Stephen Warren <swarren@nvidia.com> | Thu Apr 26 11:19:03 2012 -0600 |
| committer | Stephen Warren <swarren@nvidia.com> | Thu May 03 14:49:08 2012 -0600 |
| tree | 050f3475bfeeca1aa5d24923bc8d3d108a938afd | |
| parent | b46b0b54dea200973ce380369beb192b136d8934 [diff] |
ARM: dt: tegra seaboard: fix I2C2 SCL rate This I2C bus is used for EDID/DDC reads and other "slow" I2C devices. This requires a 100KHz SCL (clock) rate. Signed-off-by: Stephen Warren <swarren@nvidia.com>