iommu: Support MMU500 Deep Prefetch errata workaround
If deep prefetch is enabled, but not all page table entries in the
prefetch window are valid, improper permissions may be cached for
valid entries in this window. Ensure the start and end of all mapped
buffers are aligned to 16kB to prevent this issue.
Change-Id: I53bc18529b77c775338c477487333b404b225c58
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
diff --git a/drivers/iommu/dma-mapping-fast.c b/drivers/iommu/dma-mapping-fast.c
index 1ddf0dd..73090df 100644
--- a/drivers/iommu/dma-mapping-fast.c
+++ b/drivers/iommu/dma-mapping-fast.c
@@ -20,6 +20,9 @@
#include <linux/slab.h>
#include <linux/vmalloc.h>
+#include <soc/qcom/secure_buffer.h>
+#include <linux/arm-smmu-errata.h>
+
/* some redundant definitions... :( TODO: move to io-pgtable-fast.h */
#define FAST_PAGE_SHIFT 12
#define FAST_PAGE_SIZE (1UL << FAST_PAGE_SHIFT)
@@ -152,9 +155,18 @@
unsigned long attrs,
size_t size)
{
- unsigned long bit, prev_search_start, nbits = size >> FAST_PAGE_SHIFT;
- unsigned long align = (1 << get_order(size)) - 1;
+ unsigned long bit, prev_search_start, nbits;
+ unsigned long align;
+ unsigned long guard_len;
+ dma_addr_t iova;
+ if (mapping->min_iova_align)
+ guard_len = ALIGN(size, mapping->min_iova_align) - size;
+ else
+ guard_len = 0;
+
+ nbits = (size + guard_len) >> FAST_PAGE_SHIFT;
+ align = (1 << get_order(size + guard_len)) - 1;
bit = bitmap_find_next_zero_area(
mapping->bitmap, mapping->num_4k_pages, mapping->next_start,
nbits, align);
@@ -191,7 +203,16 @@
av8l_fast_clear_stale_ptes(mapping->pgtbl_pmds, skip_sync);
}
- return (bit << FAST_PAGE_SHIFT) + mapping->base;
+ iova = (bit << FAST_PAGE_SHIFT) + mapping->base;
+ if (guard_len &&
+ iommu_map(mapping->domain, iova + size,
+ page_to_phys(mapping->guard_page),
+ guard_len, ARM_SMMU_GUARD_PROT)) {
+
+ bitmap_clear(mapping->bitmap, bit, nbits);
+ return DMA_ERROR_CODE;
+ }
+ return iova;
}
/*
@@ -285,7 +306,16 @@
dma_addr_t iova, size_t size)
{
unsigned long start_bit = (iova - mapping->base) >> FAST_PAGE_SHIFT;
- unsigned long nbits = size >> FAST_PAGE_SHIFT;
+ unsigned long nbits;
+ unsigned long guard_len;
+
+ if (mapping->min_iova_align)
+ guard_len = ALIGN(size, mapping->min_iova_align) - size;
+ else
+ guard_len = 0;
+ nbits = (size + guard_len) >> FAST_PAGE_SHIFT;
+
+ iommu_unmap(mapping->domain, iova + size, guard_len);
/*
* We don't invalidate TLBs on unmap. We invalidate TLBs on map
@@ -856,6 +886,28 @@
spin_unlock_irqrestore(&mapping->lock, flags);
}
+static int fast_smmu_errata_init(struct dma_iommu_mapping *mapping)
+{
+ struct dma_fast_smmu_mapping *fast = mapping->fast;
+ int vmid = VMID_HLOS;
+ int min_iova_align = 0;
+
+ iommu_domain_get_attr(mapping->domain,
+ DOMAIN_ATTR_QCOM_MMU500_ERRATA_MIN_ALIGN,
+ &min_iova_align);
+ iommu_domain_get_attr(mapping->domain, DOMAIN_ATTR_SECURE_VMID, &vmid);
+ if (vmid >= VMID_LAST || vmid < 0)
+ vmid = VMID_HLOS;
+
+ if (min_iova_align) {
+ fast->min_iova_align = ARM_SMMU_MIN_IOVA_ALIGN;
+ fast->guard_page = arm_smmu_errata_get_guard_page(vmid);
+ if (!fast->guard_page)
+ return -ENOMEM;
+ }
+ return 0;
+}
+
/**
* fast_smmu_init_mapping
* @dev: valid struct device pointer
@@ -884,6 +936,9 @@
mapping->fast->domain = domain;
mapping->fast->dev = dev;
+ if (fast_smmu_errata_init(mapping))
+ goto release_mapping;
+
fast_smmu_reserve_pci_windows(dev, mapping->fast);
if (iommu_domain_get_attr(domain, DOMAIN_ATTR_PGTBL_INFO,