| commit | 247c445c0fbd52c77e497ff5bfcf0dceb8afea8d | [log] [tgz] |
|---|---|---|
| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | Wed May 09 20:38:35 2012 +0530 |
| committer | Santosh Shilimkar <santosh.shilimkar@ti.com> | Mon Jul 09 19:14:39 2012 +0530 |
| tree | 3334a9cd1b573fa5d447cf0876e8904d21aef105 | |
| parent | e17933c2c0173ec19aa2450e4be79b7adfd52224 [diff] |
ARM: OMAP5: Add the WakeupGen IP updates OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5. - Additional 32 interrupt support is added w.r.t OMAP4 design. - The AUX CORE boot registers are now made accessible from non-secure SW. - SAR offset are changed and PTMSYNC* registers are removed from SAR. Patch updates the WakeupGen code accordingly. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>