tree 068f42396cd32eb980fcbf94afc8a5ea5275d8d0
parent 29b4817d4018df78086157ea3a55c1d9424a7cfc
author Geert Uytterhoeven <geert+renesas@glider.be> 1467038887 +0200
committer Geert Uytterhoeven <geert+renesas@glider.be> 1470729227 +0200

clk: renesas: r8a7796: Add watchdog core clocks

Add all core clocks related to the Watchdog Timer (WDT) controller on
the Renesas R-Car M3-W (r8a7796) SoC: OSC, Internal RCLK, and RCLK.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>