clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL
Add clock functions to initialize, enable, and disable the FCPU clock
shapers, based on the FCPU voltage rail state. These will be used by
the DFLL clocksource driver code.
This version of the patch contains a fix for a problem noticed by Andrew
Chew <achew@nvidia.com>, where some of the FINETRIM_R bitfields were
incorrectly defined.
Based on code originally written by Aleksandr Frid <afrid@nvidia.com>.
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Andrew Chew <achew@nvidia.com>
Reviewed-by: Andrew Chew <achew@nvidia.com>
Cc: Matthew Longnecker <mlongnecker@nvidia.com>
Cc: Aleksandr Frid <afrid@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index e01ac46..554814c 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -587,6 +587,10 @@
void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
struct clk *clks[], int clk_max);
+void tegra114_clock_tune_cpu_trimmers_high(void);
+void tegra114_clock_tune_cpu_trimmers_low(void);
+void tegra114_clock_tune_cpu_trimmers_init(void);
+
typedef void (*tegra_clk_apply_init_table_func)(void);
extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;