tree d78d6e68100f88c84a16ff6468fff380e0d5b2d2
parent 02afa2a01b74ed3e8f3a85be11919b33f4ad4f02
author Sujith <Sujith.Manoharan@atheros.com> 1268816122 +0530
committer John W. Linville <linville@tuxdriver.com> 1269377416 -0400

ath9k_hw: always set the core clock for AR9271

When initializing the PLL on AR9271 we always need
to set the core clock to 117MHz. While at it remove
the baud rate settings for the serial device on the
AR9271, the default settings work well unless you
want to customize it.

Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>