staging: fbtft: Use standard MIPI DCS command defines for ili9340
This patch makes use of the standard MIPI Display Command Set to remove
some of the magic constants found in source code.
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
diff --git a/drivers/staging/fbtft/fb_ili9340.c b/drivers/staging/fbtft/fb_ili9340.c
index e0e2539..9b24c9e 100644
--- a/drivers/staging/fbtft/fb_ili9340.c
+++ b/drivers/staging/fbtft/fb_ili9340.c
@@ -19,6 +19,7 @@
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/delay.h>
+#include <video/mipi_display.h>
#include "fbtft.h"
@@ -53,7 +54,7 @@
/* COLMOD: Pixel Format Set */
/* 16 bits/pixel */
- write_reg(par, 0x3A, 0x55);
+ write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, 0x55);
/* Frame Rate Control */
/* Division ratio = fosc, Frame Rate = 79Hz */
@@ -65,8 +66,8 @@
/* Gamma Function Disable */
write_reg(par, 0xF2, 0x00);
- /* Gamma curve selected */
- write_reg(par, 0x26, 0x01);
+ /* Gamma curve selection */
+ write_reg(par, MIPI_DCS_SET_GAMMA_CURVE, 0x01);
/* Positive Gamma Correction */
write_reg(par, 0xE0,
@@ -78,27 +79,24 @@
0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, 0x31, 0xC1,
0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F);
- /* Sleep OUT */
- write_reg(par, 0x11);
+ write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE);
mdelay(120);
- /* Display ON */
- write_reg(par, 0x29);
+ write_reg(par, MIPI_DCS_SET_DISPLAY_ON);
return 0;
}
static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
{
- /* Column address */
- write_reg(par, 0x2A, xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
+ write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
+ xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);
- /* Row address */
- write_reg(par, 0x2B, ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
+ write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
+ ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);
- /* Memory write */
- write_reg(par, 0x2C);
+ write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
}
#define ILI9340_MADCTL_MV 0x20
@@ -123,7 +121,7 @@
break;
}
/* Memory Access Control */
- write_reg(par, 0x36, val | (par->bgr << 3));
+ write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, val | (par->bgr << 3));
return 0;
}