268aebaa2410152bf91ea1ede6b284ff8138822d - kernel/msm-4.9

commit	268aebaa2410152bf91ea1ede6b284ff8138822d	[log] [tgz]
author	Xing Zheng <zhengxing@rock-chips.com>	Wed Mar 09 10:37:03 2016 +0800
committer	Heiko Stuebner <heiko@sntech.de>	Sun Mar 27 13:03:33 2016 +0200
tree	f3831b0a1978eb3eeb0abf22d90e6c839a66f6f0
parent	9387bfd19b457085189d918ef117ffd63c4d67a0 [diff]

clk: rockchip: allow varying mux parameters for cpuclk pll-sources

Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.

Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

drivers/clk/rockchip/clk-cpu.c[diff]
drivers/clk/rockchip/clk-rk3036.c[diff]
drivers/clk/rockchip/clk-rk3188.c[diff]
drivers/clk/rockchip/clk-rk3228.c[diff]
drivers/clk/rockchip/clk-rk3288.c[diff]
drivers/clk/rockchip/clk-rk3368.c[diff]
drivers/clk/rockchip/clk.h[diff]

7 files changed

tree: f3831b0a1978eb3eeb0abf22d90e6c839a66f6f0