tree 3789a48dbf291811980cde03016eed2dfcde419a
parent 0ce7d58ee0d814622bf7b4700925455dd4960ddd
author Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> 1385546873 +0000
committer Ralf Baechle <ralf@linux-mips.org> 1390418341 +0100

MIPS: Add support for interAptiv cores

The interAptiv is a power-efficient multi-core microprocessor
for use in system-on-chip (SoC) applications. The interAptiv combines
a multi-threading pipeline with a coherence manager to deliver improved
computational throughput and power efficiency. The interAptiv can
contain one to four MIPS32R3 interAptiv cores, system level
coherence manager with L2 cache, optional coherent I/O port,
and optional floating point unit.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6163/