serial: sh-sci: Add more register documentation
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Simon Horman <horms@verge.net.au>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index 22b3640..6c5e3bb 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -10,45 +10,59 @@
#define SCIx_NOT_SUPPORTED (-1)
-#define SCSCR_TIE (1 << 7)
-#define SCSCR_RIE (1 << 6)
-#define SCSCR_TE (1 << 5)
-#define SCSCR_RE (1 << 4)
-#define SCSCR_REIE (1 << 3) /* not supported by all parts */
-#define SCSCR_TOIE (1 << 2) /* not supported by all parts */
-#define SCSCR_CKE1 (1 << 1)
-#define SCSCR_CKE0 (1 << 0)
+/* SCSMR (Serial Mode Register) */
+#define SCSMR_CHR (1 << 6) /* 7-bit Character Length */
+#define SCSMR_PE (1 << 5) /* Parity Enable */
+#define SCSMR_ODD (1 << 4) /* Odd Parity */
+#define SCSMR_STOP (1 << 3) /* Stop Bit Length */
+#define SCSMR_CKS 0x0003 /* Clock Select */
-/* SCxSR SCI */
-#define SCI_TDRE 0x80
-#define SCI_RDRF 0x40
-#define SCI_ORER 0x20
-#define SCI_FER 0x10
-#define SCI_PER 0x08
-#define SCI_TEND 0x04
+/* Serial Control Register (@ = not supported by all parts) */
+#define SCSCR_TIE (1 << 7) /* Transmit Interrupt Enable */
+#define SCSCR_RIE (1 << 6) /* Receive Interrupt Enable */
+#define SCSCR_TE (1 << 5) /* Transmit Enable */
+#define SCSCR_RE (1 << 4) /* Receive Enable */
+#define SCSCR_REIE (1 << 3) /* Receive Error Interrupt Enable @ */
+#define SCSCR_TOIE (1 << 2) /* Timeout Interrupt Enable @ */
+#define SCSCR_CKE1 (1 << 1) /* Clock Enable 1 */
+#define SCSCR_CKE0 (1 << 0) /* Clock Enable 0 */
+/* SCIFA/SCIFB only */
+#define SCSCR_TDRQE (1 << 15) /* Tx Data Transfer Request Enable */
+#define SCSCR_RDRQE (1 << 14) /* Rx Data Transfer Request Enable */
+
+/* SCxSR (Serial Status Register) on SCI */
+#define SCI_TDRE 0x80 /* Transmit Data Register Empty */
+#define SCI_RDRF 0x40 /* Receive Data Register Full */
+#define SCI_ORER 0x20 /* Overrun Error */
+#define SCI_FER 0x10 /* Framing Error */
+#define SCI_PER 0x08 /* Parity Error */
+#define SCI_TEND 0x04 /* Transmit End */
#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
-/* SCxSR SCIF, HSCIF */
-#define SCIF_ER 0x0080
-#define SCIF_TEND 0x0040
-#define SCIF_TDFE 0x0020
-#define SCIF_BRK 0x0010
-#define SCIF_FER 0x0008
-#define SCIF_PER 0x0004
-#define SCIF_RDF 0x0002
-#define SCIF_DR 0x0001
+/* SCxSR (Serial Status Register) on SCIF, HSCIF */
+#define SCIF_ER 0x0080 /* Receive Error */
+#define SCIF_TEND 0x0040 /* Transmission End */
+#define SCIF_TDFE 0x0020 /* Transmit FIFO Data Empty */
+#define SCIF_BRK 0x0010 /* Break Detect */
+#define SCIF_FER 0x0008 /* Framing Error */
+#define SCIF_PER 0x0004 /* Parity Error */
+#define SCIF_RDF 0x0002 /* Receive FIFO Data Full */
+#define SCIF_DR 0x0001 /* Receive Data Ready */
#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
-/* SCSPTR, optional */
-#define SCSPTR_RTSIO (1 << 7)
-#define SCSPTR_CTSIO (1 << 5)
-#define SCSPTR_SPB2IO (1 << 1)
-#define SCSPTR_SPB2DT (1 << 0)
+/* SCFCR (FIFO Control Register) */
+#define SCFCR_LOOP (1 << 0) /* Loopback Test */
+
+/* SCSPTR (Serial Port Register), optional */
+#define SCSPTR_RTSIO (1 << 7) /* Serial Port RTS Pin Input/Output */
+#define SCSPTR_CTSIO (1 << 5) /* Serial Port CTS Pin Input/Output */
+#define SCSPTR_SPB2IO (1 << 1) /* Serial Port Break Input/Output */
+#define SCSPTR_SPB2DT (1 << 0) /* Serial Port Break Data */
/* HSSRR HSCIF */
-#define HSCIF_SRE 0x8000
+#define HSCIF_SRE 0x8000 /* Sampling Rate Register Enable */
enum {
SCIx_PROBE_REGTYPE,
@@ -73,10 +87,19 @@
* Not all registers will exist on all parts.
*/
enum {
- SCSMR, SCBRR, SCSCR, SCxSR,
- SCFCR, SCFDR, SCxTDR, SCxRDR,
- SCLSR, SCTFDR, SCRFDR, SCSPTR,
- HSSRR,
+ SCSMR, /* Serial Mode Register */
+ SCBRR, /* Bit Rate Register */
+ SCSCR, /* Serial Control Register */
+ SCxSR, /* Serial Status Register */
+ SCFCR, /* FIFO Control Register */
+ SCFDR, /* FIFO Data Count Register */
+ SCxTDR, /* Transmit (FIFO) Data Register */
+ SCxRDR, /* Receive (FIFO) Data Register */
+ SCLSR, /* Line Status Register */
+ SCTFDR, /* Transmit FIFO Data Count Register */
+ SCRFDR, /* Receive FIFO Data Count Register */
+ SCSPTR, /* Serial Port Register */
+ HSSRR, /* Sampling Rate Register */
SCIx_NR_REGS,
};