usb: dwc3: msm: Add option to bypass SMMU stage 1
In some cases USB may need to configure SMMU to bypass stage 1
translations. This is done by setting the DOMAIN_ATTR_S1_BYPASS
attribute prior to attaching to IOMMU. Add a devicetree binding
to configure this.
Change-Id: Iea5c3e741de4bda73dc0c74c3016f0158136d64b
Signed-off-by: Jack Pham <jackp@codeaurora.org>
diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
index 18056ee..bc66690 100644
--- a/Documentation/devicetree/bindings/usb/msm-ssusb.txt
+++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt
@@ -66,6 +66,7 @@
event buffers. 1 event buffer is needed per h/w accelerated endpoint.
- qcom,pm-qos-latency: This represents max tolerable CPU latency in microsecs,
which is used as a vote by driver to get max performance in perf mode.
+- qcom,smmu-s1-bypass: If present, configure SMMU to bypass stage 1 translation.
Sub nodes:
- Sub node for "DWC3- USB3 controller".