| commit | 28dc4b63cdb96f2448a677320fcc0eb112e13e3f | [log] [tgz] |
|---|---|---|
| author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | Thu Jan 23 18:41:10 2014 -0800 |
| committer | Mark Brown <broonie@linaro.org> | Mon Feb 03 12:41:37 2014 +0000 |
| tree | 3cf5e71537e640c426db51206a9864bc0f875279 | |
| parent | 96c7c0d6f8c6e09e9123f0518130c047c5de40f6 [diff] |
ASoC: rsnd: merge SRC clock timing/setting SRC clock and timing setting register exist in SRU and ADG on Gen1. But, these are merged into ADG on Gen2. Current driver is supporting Gen1 SRC only at this point, but, above settings are set as different function. This patch merges these as preparation of Gen2 support. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@linaro.org>