| commit | 28fe2076004da062e9affac1cec98c697de53eb1 | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Mon Jan 26 16:02:48 2015 +0100 |
| committer | Thierry Reding <treding@nvidia.com> | Thu Apr 02 18:46:16 2015 +0200 |
| tree | d40639a99dc33d82b6586b2b27c68c36bac18d46 | |
| parent | 28c23373b88bcc244b573ea45596a51e9db73d2c [diff] |
drm/tegra: sor: Registers are 32-bit Use a sized unsigned 32-bit data type (u32) to store register contents. The SOR registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding <treding@nvidia.com>