| commit | c3346ef688b9956003cd357fef0a2b8c06e72ee8 | [log] [tgz] |
|---|---|---|
| author | Sonika Jindal <sonika.jindal@intel.com> | Sat Feb 21 11:12:13 2015 +0530 |
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | Tue Mar 17 22:29:57 2015 +0100 |
| tree | d8cdeffca6910fa6ee0bcc1f402b7a1bcb9fc250 | |
| parent | a8f3ef6197979824ee117d89a26c57e347c62731 [diff] |
drm/i915/skl: Program PLL for edp1.4 intermediate frequencies v2: Making the link_clock half in switch inline with the DPLL_CTRL1_* macros (Ville) Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>