tree e9398004d1647b7082b86dcc392999de69e8e16b
parent 1c5b0538c719f52cface39f699fb5d39a50149d6
author Viresh Kumar <viresh.kumar@st.com> 1299230912 +0530
committer Vinod Koul <vinod.koul@intel.com> 1299440548 +0530

dmaengine/dw_dmac fix: use readl & writel instead of __raw_readl & __raw_writel

On ARMv7 cores, device memory mapped as Normal Non-cacheable, may not guarantee
ordered access causing failures in device drivers that do not use the mandatory
memory barriers. readl & writel versions contain necessary memory barriers for
this.

commit 79f64dbf68c8a9779a7e9a25e0a9f0217a25b57a: "ARM: 6273/1: Add barriers to
the I/O accessors if ARM_DMA_MEM_BUFFERABLE" can be referred for more
information on this.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>