tree c262b61f1785452a305e66993c7a0cfc5c99fd59
parent 0132234160ae46d8bd4677e37adb0b4366e05b1e
author Kever Yang <kever.yang@rock-chips.com> 1415866309 +0800
committer Heiko Stuebner <heiko@sntech.de> 1416094819 +0100

clk: rockchip: fix clock select order for rk3288 usbphy480m_src

According to rk3288 trm, the mux selector locate at bit[12:11]
of CRU_CLKSEL13_CON shows:
2'b00: select HOST0 USB pll clock (clk_otgphy1)
2'b01: select HOST1 USB pll clock (clk_otgphy2)
2'b10: select OTG USB pll clock   (clk_otgphy0)

The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3
- clk_otgphy0 -> USB PHY OTG
- clk_otgphy1 -> USB PHY host0
- clk_otgphy2 -> USB PHY host1

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>