| commit | 29f173e81fc7d9986fcdb45ff8ca7d1cb926ae5f | [log] [tgz] |
|---|---|---|
| author | Huaibin Yang <huaibiny@codeaurora.org> | Fri Dec 19 21:53:48 2014 -0800 |
| committer | Narendra Muppalla <NarendraM@codeaurora.org> | Wed Jan 18 18:11:40 2017 -0800 |
| tree | e1f60c058bdf8ca13175f67945b7b1d542c3c2a1 | |
| parent | e59034a7408793d783173317675e934da497f4ee [diff] |
clk: mdss: add pll common block register settings for pll 1 One subset of pll common block setting registers need to be programmed for both pll 0 and pll 1 to prevent current leakage. Change-Id: I1ba621f21b49e0e55c3840b281ca9323130465a2 Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>