mmc: sdhci-msm: force 32bit ADMA descriptors
SDCC AXI master uses 32-bit addressing so there's no need to use
64-bit descriptors. Using 32-bit descriptors instead will reduce
the memory footprint.
This change masks the 64-bit capability to force 32-bit ADMA
descriptors.
CRs-Fixed: 719303
Change-Id: Ifb8095763136bbc795227bdfcb346d1e1fae42c7
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 555aab0..eb7dc58 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -108,7 +108,7 @@
#define CORE_3_3V_SUPPORT (1 << 24)
#define CORE_3_0V_SUPPORT (1 << 25)
#define CORE_1_8V_SUPPORT (1 << 26)
-#define CORE_SYS_BUS_SUPPORT_64_BIT 28
+#define CORE_SYS_BUS_SUPPORT_64_BIT BIT(28)
#define CORE_VENDOR_SPEC_ADMA_ERR_ADDR0 0x114
#define CORE_VENDOR_SPEC_ADMA_ERR_ADDR1 0x118
@@ -2777,6 +2777,16 @@
*/
if ((major == 1) && (minor < 0x34))
msm_host->use_cdclp533 = true;
+
+ /*
+ * Mask 64-bit support for controller with 32-bit address bus so that
+ * smaller descriptor size will be used and improve memory consumption.
+ * In case bus addressing ever changes, controller version should be
+ * used in order to decide whether or not to mask 64-bit support.
+ */
+ caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
+ caps &= ~CORE_SYS_BUS_SUPPORT_64_BIT;
+ writel_relaxed(caps, host->ioaddr + CORE_VENDOR_SPEC_CAPABILITIES0);
}
static int sdhci_msm_probe(struct platform_device *pdev)