[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 65160d4..dcd6913 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -48,6 +48,22 @@
#endif /* CONFIG_MIPS_MT_SMTC */
+#if defined(CONFIG_CPU_LOONGSON2)
+/*
+ * LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
+ * unfortrunately, itlb is not totally transparent to software.
+ */
+#define FLUSH_ITLB write_c0_diag(4);
+
+#define FLUSH_ITLB_VM(vma) { if ((vma)->vm_flags & VM_EXEC) write_c0_diag(4); }
+
+#else
+
+#define FLUSH_ITLB
+#define FLUSH_ITLB_VM(vma)
+
+#endif
+
void local_flush_tlb_all(void)
{
unsigned long flags;
@@ -73,6 +89,7 @@
}
tlbw_use_hazard();
write_c0_entryhi(old_ctx);
+ FLUSH_ITLB;
EXIT_CRITICAL(flags);
}
@@ -136,6 +153,7 @@
} else {
drop_mmu_context(mm, cpu);
}
+ FLUSH_ITLB;
EXIT_CRITICAL(flags);
}
}
@@ -178,6 +196,7 @@
} else {
local_flush_tlb_all();
}
+ FLUSH_ITLB;
EXIT_CRITICAL(flags);
}
@@ -210,6 +229,7 @@
finish:
write_c0_entryhi(oldpid);
+ FLUSH_ITLB_VM(vma);
EXIT_CRITICAL(flags);
}
}
@@ -241,7 +261,7 @@
tlbw_use_hazard();
}
write_c0_entryhi(oldpid);
-
+ FLUSH_ITLB;
EXIT_CRITICAL(flags);
}
@@ -293,6 +313,7 @@
else
tlb_write_indexed();
tlbw_use_hazard();
+ FLUSH_ITLB_VM(vma);
EXIT_CRITICAL(flags);
}