tree f5cb41230739e1e277c91a97e9b8e82fa89e97e5
parent 5172c9eb89d4ea41f86ff91b15b2b0dc75ded869
author Stanimir Varbanov <stanimir.varbanov@linaro.org> 1460363922 +0300
committer Vinod Koul <vinod.koul@intel.com> 1461080492 +0530

dmaengine: qcom: bam_dma: use correct pipe FIFO size

The pipe fifo size register must instruct the bam hw
how many hw descriptors can be pushed to fifo. Currently
we instruct the hw with 32KBytes but wrap the tail in
bam_start_dma in BAM_P_EVNT_REG on 4095 i.e. 32760. This
leads to stalled transactions when the tail wraps.

Fix this by use the correct fifo size in BAM_P_FIFO_SIZES
register i.e. 32K - 8.

Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>