| commit | 2a6f06141533fc48dc4077b0b4a9e722c1b72711 | [log] [tgz] |
|---|---|---|
| author | Alexander Shiyan <shc_work@mail.ru> | Mon May 13 21:07:23 2013 +0400 |
| committer | Olof Johansson <olof@lixom.net> | Tue Jun 11 15:47:15 2013 -0700 |
| tree | be0614eda369f144636b5790bb5844bea19490a7 | |
| parent | 5c15bd28ff194b2d738f0fa408696f2684470a26 [diff] |
ARM: clps711x: Set PLL clock to zero if we work from 13 mHz source This clock will be used in audio subsystem. Since audio cannot work without PLL we should indicate this. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Olof Johansson <olof@lixom.net>