tree be0614eda369f144636b5790bb5844bea19490a7
parent 5c15bd28ff194b2d738f0fa408696f2684470a26
author Alexander Shiyan <shc_work@mail.ru> 1368464843 +0400
committer Olof Johansson <olof@lixom.net> 1370990835 -0700

ARM: clps711x: Set PLL clock to zero if we work from 13 mHz source

This clock will be used in audio subsystem. Since audio cannot work
without PLL we should indicate this.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>