| commit | 8cb289ed60668d3350dda5aa19b4fa1dce1c07f1 | [log] [tgz] |
|---|---|---|
| author | Dinh Nguyen <dinguyen@altera.com> | Wed Apr 16 15:05:15 2014 -0500 |
| committer | Dinh Nguyen <dinguyen@altera.com> | Mon May 05 22:33:18 2014 -0500 |
| tree | 2c254d8089be3b05be5db6db16f07d23ab11986d | |
| parent | 16fb4f8bd59e0e954991f624bcc53dad2052ef0d [diff] |
ARM: socfpga: dts: Add div-reg to the main_pll clocks The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a pre-divider. Update socfpga.dtsi to represent those dividers for these clocks. Re-use the "div-reg" property that was used for the socfpga-gate-clock as this is the same thing. Also update the documentation. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>