| commit | c2dae7ef99977533084006dbaaa938e4f5637b99 | [log] [tgz] |
|---|---|---|
| author | Chandan Uddaraju <chandanu@codeaurora.org> | Mon May 19 12:23:43 2014 -0700 |
| committer | Narendra Muppalla <NarendraM@codeaurora.org> | Fri Jan 13 15:35:16 2017 -0800 |
| tree | e5d89705d9da89568ccd61766022c2ec4328c1aa | |
| parent | 5a8e1ec7fcf60c6f518192ce636bb9aed000d311 [diff] |
clk: qcom: mdss: add mdss 20nm pll clock driver support Add support for new 20nm PLL clock driver to handle different DSI panel resolutions. Add separate files to support this new 20nm PHY PLL block. Change-Id: I4ee5309449f317daddba7106cb8e1829fd6e76cf Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>