tree 99988f8602280cb8380ff1cc8b9ae2055a903142
parent c2dae7ef99977533084006dbaaa938e4f5637b99
author Chandan Uddaraju <chandanu@codeaurora.org> 1403567982 -0700
committer Narendra Muppalla <NarendraM@codeaurora.org> 1484350643 -0800

clk: qcom: mdss: fix debug clock names for DSI PLL on msm8994

Fix the debug clock names to match with proper clocks for
msm8994. These clocks are part of 20nm PHY PLL configuration.

Change-Id: I709d6df80330702304b91d76ec2cad0a7f494c1e
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>