tree 57424c3745bc493aca9837f77d97ec8335bbea7f
parent a4ca2b2fe7252032022d14b4efd462161c91165b
author Bill Huang <bilhuang@nvidia.com> 1434662919 -0400
committer Thierry Reding <treding@nvidia.com> 1450355878 +0100

clk: tegra: Read correct IDDQ register in PLL_SS registration

This fixes a bug in tegra_clk_register_pllss() which mistakenly assume
the IDDQ register is the PLL base address.

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>