tree b7d5e28e4da11607c74a7ed99c3bd2f93473a8fd
parent 2de5c00ac06c8983ab33ad51a8341584f1cf42c3
author Will Deacon <will.deacon@arm.com> 1285595715 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1285595856 +0100

ARM: 6411/1: vexpress: set RAM latencies to 1 cycle for PL310 on ct-ca9x4 tile

The PL310 on the ct-ca9x4 tile for the Versatile Express does not need
to add additional latency when accessing its cache RAMs. Unfortunately,
the boot monitor sets this up for an 8-cycle delay on reads and writes,
resulting in greatly reduced memory performance when the L2 cache is
enabled.

This patch sets the L2 RAM latencies to the correct value of 1 cycle
on the ct-ca9x4 tile before enabling the L2 cache.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>