| commit | 2ec35fd503bf6367ba55ed94dcb68edfe0d26e6a | [log] [tgz] |
|---|---|---|
| author | Gabe Black <gabeblack@chromium.org> | Thu Dec 26 16:44:21 2013 -0800 |
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | Mon Feb 17 16:18:02 2014 +0200 |
| tree | 80532460e0a1598b4382f2e7a42287c075f758c7 | |
| parent | 2edf3e035302776e4756e446baf3b6c7b94c3698 [diff] |
clk: tegra: Fix PLLP rate table This table had settings for 216MHz, but PLLP is (and is supposed to be) configured at 408MHz. If that table is used and PLLP_BASE_OVRRIDE is not set, the kernel will panic in clk_pll_recalc_rate(). Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>