| commit | 2f85f97e460a4bcfad678151fcc13dbf0b8181b3 | [log] [tgz] |
|---|---|---|
| author | Ajay Kumar <ajaykumar.rs@samsung.com> | Mon Nov 05 16:47:00 2012 +0900 |
| committer | Jingoo Han <jg1.han@samsung.com> | Thu Nov 29 10:33:28 2012 +0900 |
| tree | 3a0f87511387925ff9ad5f502f1edfce821d468d | |
| parent | 22ce19cb43e2df5b0b17159e94244d1151ea250b [diff] |
video: exynos_dp: Fix incorrect setting for INT_CTL INT_CTL register contains bits INT_POL0 and INT_POL1, and not INT_POL. This patch fixes the wrong register setting for INT_CTL. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com>