tree 3a0f87511387925ff9ad5f502f1edfce821d468d
parent 22ce19cb43e2df5b0b17159e94244d1151ea250b
author Ajay Kumar <ajaykumar.rs@samsung.com> 1352101620 +0900
committer Jingoo Han <jg1.han@samsung.com> 1354152808 +0900

video: exynos_dp: Fix incorrect setting for INT_CTL

INT_CTL register contains bits INT_POL0 and INT_POL1, and not INT_POL.
This patch fixes the wrong register setting for INT_CTL.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Jingoo Han <jg1.han@samsung.com>