[ARM] msm: core platform support for ARCH_MSM7X00A
- core header files for arch-msm
- Kconfig and Makefiles to enable ARCH_MSM7X00A builds
- MSM7X00A specific arch_idle
- peripheral iomap and irq number definitions
Signed-off-by: Brian Swetland <swetland@google.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a04f507..89c3811 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -409,6 +409,17 @@
help
Support for TI's OMAP platform (OMAP1 and OMAP2).
+config ARCH_MSM7X00A
+ bool "Qualcomm MSM7X00A"
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ help
+ Support for Qualcomm MSM7X00A based systems. This runs on the ARM11
+ apps processor of the MSM7X00A and depends on a shared memory
+ interface to the ARM9 modem processor which runs the baseband stack
+ and controls some vital subsystems (clock and power control, etc).
+ <http://www.cdmatech.com/products/msm7200_chipset_solution.jsp>
+
endchoice
source "arch/arm/mach-clps711x/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 35e56c9..dd220d1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -139,6 +139,7 @@
machine-$(CONFIG_ARCH_KS8695) := ks8695
incdir-$(CONFIG_ARCH_MXC) := mxc
machine-$(CONFIG_ARCH_MX3) := mx3
+ machine-$(CONFIG_ARCH_MSM7X00A) := msm
ifeq ($(CONFIG_ARCH_EBSA110),y)
# This is what happens if you forget the IOCS16 line.
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
new file mode 100644
index 0000000..feb9e46
--- /dev/null
+++ b/arch/arm/mach-msm/Makefile
@@ -0,0 +1,2 @@
+obj-y += io.o idle.o
+
diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot
new file mode 100644
index 0000000..24dfbf8
--- /dev/null
+++ b/arch/arm/mach-msm/Makefile.boot
@@ -0,0 +1,3 @@
+ zreladdr-y := 0x10008000
+params_phys-y := 0x10000100
+initrd_phys-y := 0x10800000
diff --git a/arch/arm/mach-msm/idle.S b/arch/arm/mach-msm/idle.S
new file mode 100644
index 0000000..2b1cb7f
--- /dev/null
+++ b/arch/arm/mach-msm/idle.S
@@ -0,0 +1,36 @@
+/* linux/include/asm-arm/arch-msm/idle.S
+ *
+ * Idle processing for MSM7K - work around bugs with SWFI.
+ *
+ * Copyright (c) 2007 QUALCOMM Incorporated.
+ * Copyright (C) 2007 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ENTRY(arch_idle)
+#ifdef CONFIG_MSM7X00A_IDLE
+ mrc p15, 0, r1, c1, c0, 0 /* read current CR */
+ bic r0, r1, #(1 << 2) /* clear dcache bit */
+ bic r0, r0, #(1 << 12) /* clear icache bit */
+ mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
+
+ mov r0, #0 /* prepare wfi value */
+ mcr p15, 0, r0, c7, c10, 0 /* flush the cache */
+ mcr p15, 0, r0, c7, c10, 4 /* memory barrier */
+ mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
+
+ mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */
+#endif
+ mov pc, lr
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
new file mode 100644
index 0000000..c39edb9
--- /dev/null
+++ b/arch/arm/mach-msm/io.c
@@ -0,0 +1,85 @@
+/* arch/arm/mach-msm/io.c
+ *
+ * MSM7K io support
+ *
+ * Copyright (C) 2007 Google, Inc.
+ * Author: Brian Swetland <swetland@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <asm/arch/msm_iomap.h>
+#include <asm/mach/map.h>
+
+#include <asm/arch/board.h>
+
+#define MSM_DEVICE(name) { \
+ .virtual = MSM_##name##_BASE, \
+ .pfn = __phys_to_pfn(MSM_##name##_PHYS), \
+ .length = MSM_##name##_SIZE, \
+ .type = MT_DEVICE_NONSHARED, \
+ }
+
+static struct map_desc msm_io_desc[] __initdata = {
+ MSM_DEVICE(VIC),
+ MSM_DEVICE(CSR),
+ MSM_DEVICE(GPT),
+ MSM_DEVICE(DMOV),
+ MSM_DEVICE(UART1),
+ MSM_DEVICE(UART2),
+ MSM_DEVICE(UART3),
+ MSM_DEVICE(I2C),
+ MSM_DEVICE(GPIO1),
+ MSM_DEVICE(GPIO2),
+ MSM_DEVICE(HSUSB),
+ MSM_DEVICE(CLK_CTL),
+ MSM_DEVICE(PMDH),
+ MSM_DEVICE(EMDH),
+ MSM_DEVICE(MDP),
+ {
+ .virtual = MSM_SHARED_RAM_BASE,
+ .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
+ .length = MSM_SHARED_RAM_SIZE,
+ .type = MT_DEVICE,
+ },
+};
+
+void __init msm_map_common_io(void)
+{
+ /* Make sure the peripheral register window is closed, since
+ * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
+ * pages are peripheral interface or not.
+ */
+ asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
+
+ iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc));
+}
+
+void __iomem *
+__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+{
+ if (mtype == MT_DEVICE) {
+ /* The peripherals in the 88000000 - D0000000 range
+ * are only accessable by type MT_DEVICE_NONSHARED.
+ * Adjust mtype as necessary to make this "just work."
+ */
+ if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))
+ mtype = MT_DEVICE_NONSHARED;
+ }
+
+ return __arm_ioremap(phys_addr, size, mtype);
+}
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 7868f4d..bc2ca3c 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -345,8 +345,9 @@
# ARMv6
config CPU_V6
bool "Support ARM V6 processor"
- depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3
+ depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A
default y if ARCH_MX3
+ default y if ARCH_MSM7X00A
select CPU_32v6
select CPU_ABRT_EV6
select CPU_CACHE_V6