Blackfin arch: setup aliases for some core Core A MMRs
setup aliases for some core Core A MMRs to ease porting in cases
where common code would actually want Core A (or Core B MMR is reserved)
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 89150ec..0f2dc6e 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -52,6 +52,10 @@
#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
#define CHIPID 0xFFC00014 /* Chip ID Register */
+/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
+#define SWRST SICA_SWRST
+#define SYSCR SICA_SYSCR
+
/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define SICA_SWRST 0xFFC00100 /* Software Reset register */
#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */