/*
 * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/msm-clocks-8953.h>

&soc {
	i2c@78b7000 { /* BLSP1 QUP3 */
		status = "okay";
		synaptics@4b {
			compatible = "synaptics,dsx-i2c";
			reg = <0x4b>;
			interrupt-parent = <&tlmm>;
			interrupts = <65 0x2008>;
			vdd_ana-supply = <&vdd_vreg>;
			vcc_i2c-supply = <&pm8953_l6>;
			synaptics,pwr-reg-name = "vdd_ana";
			synaptics,bus-reg-name = "vcc_i2c";
			synaptics,irq-gpio = <&tlmm 65 0x2008>;
			synaptics,irq-on-state = <0>;
			synaptics,irq-flags = <0x2008>;
			synaptics,power-delay-ms = <200>;
			synaptics,reset-delay-ms = <200>;
			synaptics,max-y-for-2d = <1919>;
			synaptics,cap-button-codes = <139 158 172>;
			synaptics,vir-button-codes = <139 180 2000 320 160
						      158 540 2000 320 160
						      172 900 2000 320 160>;
			synaptics,resume-in-workqueue;
			/* Underlying clocks used by secure touch */
			clock-names = "iface_clk", "core_clk";
			clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
				 <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>;
		};
	};

	vdd_vreg: vdd_vreg {
		compatible = "regulator-fixed";
		status = "ok";
		regulator-name = "vdd_vreg";
	};

	gpio_keys {
		compatible = "gpio-keys";
		label = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&gpio_key_active>;

		vol_up {
			label = "volume_up";
			gpios = <&tlmm 85 0x1>;
			linux,input-type = <1>;
			linux,code = <115>;
			debounce-interval = <15>;
			linux,can-disable;
			gpio-key,wakeup;
		};
	};
};

&blsp1_uart0 {
	status = "ok";
	pinctrl-names = "default";
	pinctrl-0 = <&uart_console_active>;
};

&pm8953_gpios {
	nfc_clk {
		nfc_clk_default: nfc_clk_default {
			pins = "gpio2";
			function = "normal";
			input-enable;
			power-source = <1>;
		};
	};
};

&i2c_5 { /* BLSP2 QUP1 (NFC) */
	#address-cells = <1>;
	#size-cells = <0>;

	status = "ok";
	nq@28 {
		compatible = "qcom,nq-nci";
		reg = <0x28>;
		qcom,nq-irq = <&tlmm 17 0x00>;
		qcom,nq-ven = <&tlmm 16 0x00>;
		qcom,nq-firm = <&tlmm 62 0x00>;
		qcom,nq-clkreq = <&pm8953_gpios 2 0x00>;
		qcom,nq-esepwr = <&tlmm 141 0x00>;
		interrupt-parent = <&tlmm>;
		qcom,clk-src = "BBCLK2";
		interrupts = <17 0>;
		interrupt-names = "nfc_irq";
		pinctrl-names = "nfc_active", "nfc_suspend";
		pinctrl-0 = <&nfc_int_active &nfc_disable_active
						&nfc_clk_default>;
		pinctrl-1 = <&nfc_int_suspend &nfc_disable_suspend>;
		clocks = <&clock_gcc clk_bb_clk2_pin>;
		clock-names = "ref_clk";
	};
};

&sdhc_1 {
	/* device core power supply */
	vdd-supply = <&pm8953_l8>;
	qcom,vdd-voltage-level = <2900000 2900000>;
	qcom,vdd-current-level = <200 570000>;

	/* device communication power supply */
	vdd-io-supply = <&pm8953_l5>;
	qcom,vdd-io-always-on;
	qcom,vdd-io-lpm-sup;
	qcom,vdd-io-voltage-level = <1800000 1800000>;
	qcom,vdd-io-current-level = <200 325000>;

	pinctrl-names = "active", "sleep";
	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on  &sdc1_rclk_on>;
	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;

	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000
								384000000>;
	qcom,nonremovable;
	qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";

	status = "ok";
};

&sdhc_2 {
	/* device core power supply */
	vdd-supply = <&pm8953_l11>;
	qcom,vdd-voltage-level = <2950000 2950000>;
	qcom,vdd-current-level = <15000 800000>;

	/* device communication power supply */
	vdd-io-supply = <&pm8953_l12>;
	qcom,vdd-io-voltage-level = <1800000 2950000>;
	qcom,vdd-io-current-level = <200 22000>;

	pinctrl-names = "active", "sleep";
	pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;

	#address-cells = <0>;
	interrupt-parent = <&sdhc_2>;
	interrupts = <0 1 2>;
	#interrupt-cells = <1>;
	interrupt-map-mask = <0xffffffff>;
	interrupt-map = <0 &intc 0 125 0
		1 &intc 0 221 0
		2 &tlmm 133 0>;
	interrupt-names = "hc_irq", "pwr_irq", "status_irq";
	cd-gpios = <&tlmm 133 0x1>;

	qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
								200000000>;
	qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";

	status = "ok";
};