drm/msm/sde: support ubwc 2.0 feature
This patch provides register programming support for UBWC 2.0
compression on SSPP and WB components.
CRs-Fixed: 2019304
Change-Id: If33fa5b2eb97cf59d7a32745a6d82da124103af3
Signed-off-by: Clarence Ip <cip@codeaurora.org>
diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index 5eee0c9..c38b45c 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -117,6 +117,11 @@
type.
- qcom,sde-highest-bank-bit: A u32 property to indicate GPU/Camera/Video highest memory
bank bit used for tile format buffers.
+- qcom,sde-ubwc-version: Property to specify the UBWC feature version.
+- qcom,sde-ubwc-static: Property to specify the default UBWC static
+ configuration value.
+- qcom,sde-ubwc-swizzle: Property to specify the default UBWC swizzle
+ configuration value.
- qcom,sde-panic-per-pipe: Boolean property to indicate if panic signal
control feature is available on each source pipe.
- qcom,sde-has-src-split: Boolean property to indicate if source split
@@ -388,6 +393,9 @@
qcom,sde-sspp-linewidth = <2560>;
qcom,sde-mixer-blendstages = <0x7>;
qcom,sde-highest-bank-bit = <0x2>;
+ qcom,sde-ubwc-version = <0x100>;
+ qcom,sde-ubwc-static = <0x100>;
+ qcom,sde-ubwc-swizzle = <0>;
qcom,sde-panic-per-pipe;
qcom,sde-has-cdp;
qcom,sde-has-src-split;
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
index bdab758..5187627 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
@@ -379,7 +379,7 @@
}
if (SDE_FORMAT_IS_UBWC(fmt) &&
- !(wb_cfg->features & BIT(SDE_WB_UBWC_1_0))) {
+ !(wb_cfg->features & BIT(SDE_WB_UBWC))) {
SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
return -EINVAL;
}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index 9018581..369d5d1 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -43,6 +43,15 @@
/* max bank bit for macro tile and ubwc format */
#define DEFAULT_SDE_HIGHEST_BANK_BIT 15
+/* default ubwc version */
+#define DEFAULT_SDE_UBWC_VERSION SDE_HW_UBWC_VER_10
+
+/* default ubwc static config register value */
+#define DEFAULT_SDE_UBWC_STATIC 0x0
+
+/* default ubwc swizzle register value */
+#define DEFAULT_SDE_UBWC_SWIZZLE 0x0
+
/* default hardware block size if dtsi entry is not present */
#define DEFAULT_SDE_HW_BLOCK_LEN 0x100
@@ -97,6 +106,9 @@
MIXER_BLEND,
WB_LINEWIDTH,
BANK_BIT,
+ UBWC_VERSION,
+ UBWC_STATIC,
+ UBWC_SWIZZLE,
QSEED_TYPE,
CSC_TYPE,
PANIC_PER_PIPE,
@@ -287,6 +299,9 @@
{MIXER_BLEND, "qcom,sde-mixer-blendstages", false, PROP_TYPE_U32},
{WB_LINEWIDTH, "qcom,sde-wb-linewidth", false, PROP_TYPE_U32},
{BANK_BIT, "qcom,sde-highest-bank-bit", false, PROP_TYPE_U32},
+ {UBWC_VERSION, "qcom,sde-ubwc-version", false, PROP_TYPE_U32},
+ {UBWC_STATIC, "qcom,sde-ubwc-static", false, PROP_TYPE_U32},
+ {UBWC_SWIZZLE, "qcom,sde-ubwc-swizzle", false, PROP_TYPE_U32},
{QSEED_TYPE, "qcom,sde-qseed-type", false, PROP_TYPE_STRING},
{CSC_TYPE, "qcom,sde-csc-type", false, PROP_TYPE_STRING},
{PANIC_PER_PIPE, "qcom,sde-panic-per-pipe", false, PROP_TYPE_BOOL},
@@ -809,6 +824,8 @@
sblk->pcc_blk.len = 0;
set_bit(SDE_SSPP_PCC, &sspp->features);
}
+
+ sblk->format_list = sde_cfg->vig_formats;
}
static void _sde_sspp_setup_rgb(struct sde_mdss_cfg *sde_cfg,
@@ -856,15 +873,21 @@
sblk->pcc_blk.len = 0;
set_bit(SDE_SSPP_PCC, &sspp->features);
}
+
+ sblk->format_list = sde_cfg->dma_formats;
}
static void _sde_sspp_setup_cursor(struct sde_mdss_cfg *sde_cfg,
struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
struct sde_prop_value *prop_value, u32 *cursor_count)
{
+ if (!IS_SDE_MAJOR_MINOR_SAME(sde_cfg->hwversion, SDE_HW_VER_300))
+ SDE_ERROR("invalid sspp type %d, xin id %d\n",
+ sspp->type, sspp->xin_id);
set_bit(SDE_SSPP_CURSOR, &sspp->features);
sblk->maxupscale = SSPP_UNITY_SCALE;
sblk->maxdwnscale = SSPP_UNITY_SCALE;
+ sblk->format_list = sde_cfg->cursor_formats;
sspp->id = SSPP_CURSOR0 + *cursor_count;
snprintf(sspp->name, SDE_HW_BLK_NAME_LEN, "sspp_%u", sspp->id);
sspp->clk_ctrl = SDE_CLK_CTRL_CURSOR0 + *cursor_count;
@@ -878,6 +901,7 @@
{
sblk->maxupscale = SSPP_UNITY_SCALE;
sblk->maxdwnscale = SSPP_UNITY_SCALE;
+ sblk->format_list = sde_cfg->dma_formats;
sspp->id = SSPP_DMA0 + *dma_count;
sspp->clk_ctrl = SDE_CLK_CTRL_DMA0 + *dma_count;
snprintf(sspp->name, SDE_HW_BLK_NAME_LEN, "sspp_%u", sspp->id);
@@ -1414,6 +1438,9 @@
set_bit(SDE_WB_TRAFFIC_SHAPER, &wb->features);
set_bit(SDE_WB_YUV_CONFIG, &wb->features);
+ if (sde_cfg->has_wb_ubwc)
+ set_bit(SDE_WB_UBWC, &wb->features);
+
for (j = 0; j < sde_cfg->mdp_count; j++) {
sde_cfg->mdp[j].clk_ctrls[wb->clk_ctrl].reg_off =
PROP_BITVALUE_ACCESS(prop_value,
@@ -1423,6 +1450,8 @@
WB_CLK_CTRL, i, 1);
}
+ wb->format_list = sde_cfg->wb_formats;
+
SDE_DEBUG(
"wb:%d xin:%d vbif:%d clk%d:%x/%d\n",
wb->id - WB_0,
@@ -2037,6 +2066,19 @@
if (!prop_exists[BANK_BIT])
cfg->mdp[0].highest_bank_bit = DEFAULT_SDE_HIGHEST_BANK_BIT;
+ cfg->ubwc_version = PROP_VALUE_ACCESS(prop_value, UBWC_VERSION, 0);
+ if (!prop_exists[UBWC_VERSION])
+ cfg->ubwc_version = DEFAULT_SDE_UBWC_VERSION;
+
+ cfg->mdp[0].ubwc_static = PROP_VALUE_ACCESS(prop_value, UBWC_STATIC, 0);
+ if (!prop_exists[UBWC_STATIC])
+ cfg->mdp[0].ubwc_static = DEFAULT_SDE_UBWC_STATIC;
+
+ cfg->mdp[0].ubwc_swizzle = PROP_VALUE_ACCESS(prop_value,
+ UBWC_SWIZZLE, 0);
+ if (!prop_exists[UBWC_SWIZZLE])
+ cfg->mdp[0].ubwc_swizzle = DEFAULT_SDE_UBWC_SWIZZLE;
+
rc = of_property_read_string(np, sde_prop[QSEED_TYPE].prop_name, &type);
if (!rc && !strcmp(type, "qseedv3")) {
cfg->qseed_type = SDE_SSPP_SCALER_QSEED3;
@@ -2154,10 +2196,9 @@
static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg,
uint32_t hw_rev)
{
- int i, rc = 0;
+ int rc = 0;
uint32_t dma_list_size, vig_list_size, wb2_list_size;
uint32_t cursor_list_size = 0;
- struct sde_sspp_sub_blks *sblk;
uint32_t index = 0;
if (IS_SDE_MAJOR_MINOR_SAME((hw_rev), SDE_HW_VER_300)) {
@@ -2239,43 +2280,17 @@
index += _sde_copy_formats(sde_cfg->wb_formats, wb2_list_size,
index, tp10_ubwc_formats,
ARRAY_SIZE(tp10_ubwc_formats));
-
- for (i = 0; i < sde_cfg->sspp_count; ++i) {
- struct sde_sspp_cfg *sspp = &sde_cfg->sspp[i];
-
- sblk = (struct sde_sspp_sub_blks *)sspp->sblk;
- switch (sspp->type) {
- case SSPP_TYPE_VIG:
- sblk->format_list = sde_cfg->vig_formats;
- break;
- case SSPP_TYPE_CURSOR:
- if (IS_SDE_MAJOR_MINOR_SAME((hw_rev), SDE_HW_VER_300))
- sblk->format_list = sde_cfg->cursor_formats;
- else
- SDE_ERROR("invalid sspp type %d, xin id %d\n",
- sspp->type, sspp->xin_id);
- break;
- case SSPP_TYPE_DMA:
- sblk->format_list = sde_cfg->dma_formats;
- break;
- default:
- SDE_ERROR("invalid sspp type %d\n", sspp->type);
- rc = -EINVAL;
- goto end;
- }
- }
-
- for (i = 0; i < sde_cfg->wb_count; ++i)
- sde_cfg->wb[i].format_list = sde_cfg->wb_formats;
-
end:
return rc;
}
-static int sde_hardware_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
+static int _sde_hardware_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
{
int rc = 0;
+ if (!sde_cfg)
+ return -EINVAL;
+
switch (hw_rev) {
case SDE_HW_VER_170:
case SDE_HW_VER_171:
@@ -2287,6 +2302,7 @@
case SDE_HW_VER_400:
/* update msm8998 and sdm845 target here */
rc = sde_hardware_format_caps(sde_cfg, hw_rev);
+ sde_cfg->has_wb_ubwc = true;
break;
}
@@ -2343,6 +2359,10 @@
sde_cfg->hwversion = hw_rev;
+ rc = _sde_hardware_caps(sde_cfg, hw_rev);
+ if (rc)
+ goto end;
+
rc = sde_parse_dt(np, sde_cfg);
if (rc)
goto end;
@@ -2397,10 +2417,6 @@
if (rc)
goto end;
- rc = sde_hardware_caps(sde_cfg, hw_rev);
- if (rc)
- goto end;
-
return sde_cfg;
end:
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index 23640bb..2b34016 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -61,6 +61,17 @@
#define SDE_COLOR_PROCESS_MINOR(version) ((version) & 0xFFFF)
/**
+ * Supported UBWC feature versions
+ */
+enum {
+ SDE_HW_UBWC_VER_10 = 0x100,
+ SDE_HW_UBWC_VER_20 = 0x200,
+ SDE_HW_UBWC_VER_30 = 0x300,
+};
+
+#define IS_UBWC_20_SUPPORTED(rev) ((rev) >= SDE_HW_UBWC_VER_20)
+
+/**
* MDP TOP BLOCK features
* @SDE_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe
* @SDE_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
@@ -207,9 +218,7 @@
* @SDE_WB_DOWNSCALE, Writeback integer downscaler,
* @SDE_WB_DITHER, Dither block
* @SDE_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc
- * @SDE_WB_UBWC_1_0, Writeback Universal bandwidth compression 1.0
- * support
- * @SDE_WB_UBWC_1_5 UBWC 1.5 support
+ * @SDE_WB_UBWC, Writeback Universal bandwidth compression
* @SDE_WB_YUV_CONFIG Writeback supports output of YUV colorspace
* @SDE_WB_PIPE_ALPHA Writeback supports pipe alpha
* @SDE_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in
@@ -225,7 +234,7 @@
SDE_WB_DOWNSCALE,
SDE_WB_DITHER,
SDE_WB_TRAFFIC_SHAPER,
- SDE_WB_UBWC_1_0,
+ SDE_WB_UBWC,
SDE_WB_YUV_CONFIG,
SDE_WB_PIPE_ALPHA,
SDE_WB_XY_ROI_OFFSET,
@@ -447,11 +456,15 @@
* @base: register base offset to mdss
* @features bit mask identifying sub-blocks/features
* @highest_bank_bit: UBWC parameter
+ * @ubwc_static: ubwc static configuration
+ * @ubwc_swizzle: ubwc default swizzle setting
* @clk_ctrls clock control register definition
*/
struct sde_mdp_cfg {
SDE_HW_BLK_INFO;
u32 highest_bank_bit;
+ u32 ubwc_static;
+ u32 ubwc_swizzle;
struct sde_clk_ctrl_reg clk_ctrls[SDE_CLK_CTRL_MAX];
};
@@ -660,12 +673,13 @@
* @max_mixer_blendstages max layer mixer blend stages or
* supported z order
* @max_wb_linewidth max writeback line width support.
- * @highest_bank_bit highest memory bit setting for tile buffers.
* @qseed_type qseed2 or qseed3 support.
* @csc_type csc or csc_10bit support.
* @smart_dma_rev Supported version of SmartDMA feature.
* @has_src_split source split feature status
* @has_cdp Client driver prefetch feature status
+ * @has_wb_ubwc UBWC feature supported on WB
+ * @ubwc_version UBWC feature version (0x0 for not supported)
* @dma_formats Supported formats for dma pipe
* @cursor_formats Supported formats for cursor pipe
* @vig_formats Supported formats for vig pipe
@@ -678,13 +692,14 @@
u32 max_mixer_width;
u32 max_mixer_blendstages;
u32 max_wb_linewidth;
- u32 highest_bank_bit;
u32 qseed_type;
u32 csc_type;
u32 smart_dma_rev;
bool has_src_split;
bool has_cdp;
bool has_dim_layer;
+ bool has_wb_ubwc;
+ u32 ubwc_version;
u32 mdss_count;
struct sde_mdss_base_cfg mdss[MAX_BLOCKS];
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
index 14230c27..71c3855 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.c
@@ -62,6 +62,7 @@
#define SSPP_SRC_CONSTANT_COLOR 0x3c
#define SSPP_EXCL_REC_CTL 0x40
+#define SSPP_UBWC_STATIC_CTRL 0x44
#define SSPP_FETCH_CONFIG 0x048
#define SSPP_DANGER_LUT 0x60
#define SSPP_SAFE_LUT 0x64
@@ -366,7 +367,11 @@
src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
SDE_REG_WRITE(c, SSPP_FETCH_CONFIG,
SDE_FETCH_CONFIG_RESET_VALUE |
- ctx->highest_bank_bit << 18);
+ ctx->mdp->highest_bank_bit << 18);
+ if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version))
+ SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+ BIT(31) | (ctx->mdp->ubwc_swizzle) |
+ (ctx->mdp->highest_bank_bit << 4));
}
opmode |= MDSS_MDP_OP_PE_OVERRIDE;
@@ -1074,6 +1079,9 @@
struct sde_hw_pipe *hw_pipe;
struct sde_sspp_cfg *cfg;
+ if (!addr || !catalog)
+ return ERR_PTR(-EINVAL);
+
hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL);
if (!hw_pipe)
return ERR_PTR(-ENOMEM);
@@ -1085,10 +1093,11 @@
}
/* Assign ops */
+ hw_pipe->catalog = catalog;
+ hw_pipe->mdp = &catalog->mdp[0];
hw_pipe->idx = idx;
hw_pipe->cap = cfg;
_setup_layer_ops(hw_pipe, hw_pipe->cap->features);
- hw_pipe->highest_bank_bit = catalog->mdp[0].highest_bank_bit;
sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
hw_pipe->hw.blk_off,
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.h b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
index a224234..2fa01e4 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
@@ -496,21 +496,23 @@
* @blk_off: pipe offset relative to mdss offset
* @length length of register block offset
* @hwversion mdss hw version number
+ * @catalog: back pointer to catalog
+ * @mdp: pointer to associated mdp portion of the catalog
* @idx: pipe index
* @type : pipe type, VIG/DMA/RGB/CURSOR, certain operations are not
* supported for each pipe type
* @pipe_hw_cap: pointer to layer_cfg
- * @highest_bank_bit:
* @ops: pointer to operations possible for this pipe
*/
struct sde_hw_pipe {
/* base */
- struct sde_hw_blk_reg_map hw;
+ struct sde_hw_blk_reg_map hw;
+ struct sde_mdss_cfg *catalog;
+ struct sde_mdp_cfg *mdp;
/* Pipe */
enum sde_sspp idx;
const struct sde_sspp_cfg *cap;
- u32 highest_bank_bit;
/* Ops */
struct sde_hw_sspp_ops ops;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_top.c b/drivers/gpu/drm/msm/sde/sde_hw_top.c
index b3fb379..a7bebc2 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_top.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_top.c
@@ -16,6 +16,7 @@
#include "sde_dbg.h"
#define SSPP_SPARE 0x28
+#define UBWC_STATIC 0x144
#define FLD_SPLIT_DISPLAY_CMD BIT(1)
#define FLD_SMART_PANEL_FREE_RUN BIT(2)
@@ -242,6 +243,25 @@
return ERR_PTR(-EINVAL);
}
+static inline void _sde_hw_mdptop_init_ubwc(void __iomem *addr,
+ const struct sde_mdss_cfg *m)
+{
+ struct sde_hw_blk_reg_map hw;
+
+ if (!addr || !m)
+ return;
+
+ if (!IS_UBWC_20_SUPPORTED(m->ubwc_version))
+ return;
+
+ memset(&hw, 0, sizeof(hw));
+ hw.base_off = addr;
+ hw.blk_off = 0x0;
+ hw.hwversion = m->hwversion;
+ hw.log_mask = SDE_DBG_MASK_TOP;
+ SDE_REG_WRITE(&hw, UBWC_STATIC, m->mdp[0].ubwc_static);
+}
+
struct sde_hw_mdp *sde_hw_mdptop_init(enum sde_mdp idx,
void __iomem *addr,
const struct sde_mdss_cfg *m)
@@ -249,6 +269,9 @@
struct sde_hw_mdp *mdp;
const struct sde_mdp_cfg *cfg;
+ if (!addr || !m)
+ return ERR_PTR(-EINVAL);
+
mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);
if (!mdp)
return ERR_PTR(-ENOMEM);
@@ -270,6 +293,8 @@
mdp->hw.blk_off, mdp->hw.blk_off + mdp->hw.length,
mdp->hw.xin_id);
+ _sde_hw_mdptop_init_ubwc(addr, m);
+
return mdp;
}
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_wb.c b/drivers/gpu/drm/msm/sde/sde_hw_wb.c
index 320b05f..98aff0f 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_wb.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_wb.c
@@ -41,6 +41,7 @@
#define WB_N16_INIT_PHASE_Y_C12 0x06C
#define WB_OUT_SIZE 0x074
#define WB_ALPHA_X_VALUE 0x078
+#define WB_UBWC_STATIC_CTRL 0x144
#define WB_CSC_BASE 0x260
#define WB_DST_ADDR_SW_STATUS 0x2B0
#define WB_CDP_CTRL 0x2B4
@@ -135,10 +136,13 @@
if (SDE_FORMAT_IS_UBWC(fmt)) {
opmode |= BIT(0);
dst_format |= BIT(31);
- if (ctx->highest_bank_bit)
- write_config |= (ctx->highest_bank_bit << 8);
+ write_config |= (ctx->mdp->highest_bank_bit << 8);
if (fmt->base.pixel_format == DRM_FORMAT_RGB565)
write_config |= 0x8;
+ if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version))
+ SDE_REG_WRITE(c, WB_UBWC_STATIC_CTRL,
+ (ctx->mdp->ubwc_swizzle << 0) |
+ (ctx->mdp->highest_bank_bit << 4));
}
if (data->is_secure)
@@ -199,6 +203,9 @@
struct sde_hw_wb *c;
struct sde_wb_cfg *cfg;
+ if (!addr || !m || !hw_mdp)
+ return ERR_PTR(-EINVAL);
+
c = kzalloc(sizeof(*c), GFP_KERNEL);
if (!c)
return ERR_PTR(-ENOMEM);
@@ -211,10 +218,11 @@
}
/* Assign ops */
+ c->catalog = m;
+ c->mdp = &m->mdp[0];
c->idx = idx;
c->caps = cfg;
_setup_wb_ops(&c->ops, c->caps->features);
- c->highest_bank_bit = m->mdp[0].highest_bank_bit;
c->hw_mdp = hw_mdp;
sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_wb.h b/drivers/gpu/drm/msm/sde/sde_hw_wb.h
index 52a5ee5..9d17fb3 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_wb.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_wb.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -62,15 +62,18 @@
/**
* struct sde_hw_wb : WB driver object
* @struct sde_hw_blk_reg_map *hw;
+ * @catalog: back pointer to catalog
+ * @mdp: pointer to associated mdp portion of the catalog
* @idx
* @wb_hw_caps
* @ops
- * @highest_bank_bit: GPU highest memory bank bit used
* @hw_mdp: MDP top level hardware block
*/
struct sde_hw_wb {
/* base */
struct sde_hw_blk_reg_map hw;
+ struct sde_mdss_cfg *catalog;
+ struct sde_mdp_cfg *mdp;
/* wb path */
int idx;
@@ -79,8 +82,6 @@
/* ops */
struct sde_hw_wb_ops ops;
- u32 highest_bank_bit;
-
struct sde_hw_mdp *hw_mdp;
};
diff --git a/drivers/gpu/drm/msm/sde/sde_wb.c b/drivers/gpu/drm/msm/sde/sde_wb.c
index 4479e5e..2220925 100644
--- a/drivers/gpu/drm/msm/sde/sde_wb.c
+++ b/drivers/gpu/drm/msm/sde/sde_wb.c
@@ -341,7 +341,7 @@
wb_dev->wb_cfg->sblk->maxlinewidth);
sde_kms_info_start(info, "features");
- if (wb_dev->wb_cfg && (wb_dev->wb_cfg->features & SDE_WB_UBWC_1_0))
+ if (wb_dev->wb_cfg && (wb_dev->wb_cfg->features & SDE_WB_UBWC))
sde_kms_info_append(info, "wb_ubwc");
sde_kms_info_stop(info);