drm/msm/sde: support ubwc 2.0 feature
This patch provides register programming support for UBWC 2.0
compression on SSPP and WB components.
CRs-Fixed: 2019304
Change-Id: If33fa5b2eb97cf59d7a32745a6d82da124103af3
Signed-off-by: Clarence Ip <cip@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
index bdab758..5187627 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
@@ -379,7 +379,7 @@
}
if (SDE_FORMAT_IS_UBWC(fmt) &&
- !(wb_cfg->features & BIT(SDE_WB_UBWC_1_0))) {
+ !(wb_cfg->features & BIT(SDE_WB_UBWC))) {
SDE_ERROR("invalid output format %x\n", fmt->base.pixel_format);
return -EINVAL;
}