drm/msm/sde: handle VSYNC_IN_EN during crtc power events
Currently VSYNC_IN_EN is closely tied with frame updates,
it is enabled during the kickoff and disabled as part of
idle power collapse sequence. This will impact vblank
request without a frame update during idle power collapse,
as the RD_PTR_IRQ will be triggered only after the wraparound.
Disable VSYNC_IN_EN during PRE_DISABLE power event, to ensure
no vsync is triggered when RSC enters mode-2. Enable it during
POST_ENABLE power event as part of encoder restore and during
virtual encoder enable to support bootup/resume cases.
Change-Id: Iea6d6e9617a9db2c2518695ff5a428a97f887a2d
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index 7be9a4d..4f204a2 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -3968,6 +3968,21 @@
}
break;
case SDE_POWER_EVENT_PRE_DISABLE:
+ drm_for_each_encoder(encoder, crtc->dev) {
+ if (encoder->crtc != crtc)
+ continue;
+ /*
+ * disable the vsync source after updating the
+ * rsc state. rsc state update might have vsync wait
+ * and vsync source must be disabled after it.
+ * It will avoid generating any vsync from this point
+ * till mode-2 entry. It is SW workaround for HW
+ * limitation and should not be removed without
+ * checking the updated design.
+ */
+ sde_encoder_control_te(encoder, false);
+ }
+
for (i = 0; i < sde_crtc->num_mixers; ++i) {
m = &sde_crtc->mixers[i];
if (!m->hw_lm || !m->hw_lm->ops.collect_misr ||