msm: camera: icp: Dynamic clock bandwidth support

Add support for IPE and BPS dynamic clock
and bandwidth for realtime streams. Add support
to set clock and bandwidth based on user request
for debug purpose. Following command is used to
provide clock rate from user.

echo "clk rate" > /sys/kernel/debug/camera_icp/icp_debug_clk

Change-Id: I9a2cfefc8227190cd79257d948d37127767e50e1
Signed-off-by: Suresh Vankadara <svankada@codeaurora.org>
diff --git a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
index f54cbdc..8ca7291 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-camera.dtsi
@@ -840,14 +840,20 @@
 			"ipe_0_axi_clk",
 			"ipe_0_clk",
 			"ipe_0_clk_src";
+		src-clock-name = "ipe_0_clk_src";
 		clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>,
 				<&clock_camcc CAM_CC_IPE_0_AREG_CLK>,
 				<&clock_camcc CAM_CC_IPE_0_AXI_CLK>,
 				<&clock_camcc CAM_CC_IPE_0_CLK>,
 				<&clock_camcc CAM_CC_IPE_0_CLK_SRC>;
 
-		clock-rates = <0 0 0 0 600000000>;
-		clock-cntl-level = "turbo";
+		clock-rates = <0 0 0 0 240000000>,
+			<0 0 0 0 404000000>,
+			<0 0 0 0 480000000>,
+			<0 0 0 0 538000000>,
+			<0 0 0 0 600000000>;
+		clock-cntl-level = "lowsvs", "svs",
+			"svs_l1", "nominal", "turbo";
 		status = "ok";
 	};
 
@@ -861,14 +867,20 @@
 			"ipe_1_axi_clk",
 			"ipe_1_clk",
 			"ipe_1_clk_src";
+		src-clock-name = "ipe_1_clk_src";
 		clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>,
 				<&clock_camcc CAM_CC_IPE_1_AREG_CLK>,
 				<&clock_camcc CAM_CC_IPE_1_AXI_CLK>,
 				<&clock_camcc CAM_CC_IPE_1_CLK>,
 				<&clock_camcc CAM_CC_IPE_1_CLK_SRC>;
 
-		clock-rates = <0 0 0 0 600000000>;
-		clock-cntl-level = "turbo";
+		clock-rates = <0 0 0 0 240000000>,
+			<0 0 0 0 404000000>,
+			<0 0 0 0 480000000>,
+			<0 0 0 0 538000000>,
+			<0 0 0 0 600000000>;
+		clock-cntl-level = "lowsvs", "svs",
+			"svs_l1", "nominal", "turbo";
 		status = "ok";
 	};
 
@@ -882,14 +894,20 @@
 			"bps_axi_clk",
 			"bps_clk",
 			"bps_clk_src";
+		src-clock-name = "bps_clk_src";
 		clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>,
 				<&clock_camcc CAM_CC_BPS_AREG_CLK>,
 				<&clock_camcc CAM_CC_BPS_AXI_CLK>,
 				<&clock_camcc CAM_CC_BPS_CLK>,
 				<&clock_camcc CAM_CC_BPS_CLK_SRC>;
 
-		clock-rates = <0 0 0 0 600000000>;
-		clock-cntl-level = "turbo";
+		clock-rates = <0 0 0 0 200000000>,
+			<0 0 0 0 404000000>,
+			<0 0 0 0 480000000>,
+			<0 0 0 0 600000000>,
+			<0 0 0 0 600000000>;
+		clock-cntl-level = "lowsvs", "svs",
+			"svs_l1", "nominal", "turbo";
 		status = "ok";
 	};